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PDF UBA2074 Data sheet ( Hoja de datos )
| Número de pieza | UBA2074 | |
| Descripción | High Voltage Full-bridge control IC | |
| Fabricantes | NXP Semiconductors | |
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UBA2074(A)
High Voltage Full-bridge control IC for CCFL backlighting
Rev. 02.0 — February 2007
Preliminary data sheet
1. General description
The UBA2074 is a high voltage IC intended to drive Cold Cathode Fluorescent Lamps
(CCFLs) for back-lighting applications. The IC contains level-shifters, bootstrap diodes
and drivers for the external full-bridge power switches.
Furthermore, the UBA2074 has a build-in HF oscillator which determines the operating
frequency, a phase shift controller for obtaining constant lamp current, and a PWM
generator which is used to set the brightness level of the CCFLs.
Multiple inverters can be synchronized to a single operating frequency, while maintaining
constant lamp current. Also, PWM dimming can be synchronized by either using the
internal PWM generator, or by using an externally applied PWM signal.
The UBA2074 is designed to operate in a very wide inverter supply voltage range. The IC
can be configured to be supplied directly from a low voltage supply up to 30 V DC. The
fullbridge voltage can range up to 550V.
The A-version has no hardswitching protection in order to suit medium voltage (e.g 60V)
full bridge systems.
2. Features
Suitable for operating in a very wide inverter supply voltage range (up to 550 V DC for
SO28 package, up to 225 V for SSOP28 package)
Wide IC supply voltage range (9 V to 30 V DC)
Suitable for synchronizing multiple inverters to a single operating frequency with equal
lamp current phase
Adjustable maximum fault timing
Integrated level-shifters
Integrated bootstrap diodes
Lamp current control
Over-voltage control
Over-current protection
Ignition failure detection
Hard-switching control (not in the A-version)
Arcing detection
Brightness level adjustment through PWM dimming
Integrated PWM generator
Free Datasheet http://www.datasheet4u.net/
1 page  
NXP Semiconductors
UBA2074(A)
High Voltage Full-bridge control IC for CCFL backlighting
Table 2: Pin description …continued
Symbol Pin
CSWP 9
CPWM 10
SYNC
11
nonFAULT 12
PWMa
PMWd
13
14
GHB
FSB
15
16
SHB
NC
EN
VDC
VDD
GLB
PGND
GLA
NC
SHA
FSA
17
18
19
20
21
22
23
24
25
26
27
GHA
28
Description
Function
phase-shift sweep
capacitor
A capacitor must be connected between this pin and the signal ground. It sets
the time in which the phase difference between bridge halve A and bridge
halve B is swept down from regulation level to zero or swept up from zero to
regulation level during PWM dimming.
PWM timing capacitor If a capacitor is connected between this pin and the signal ground, it sets the
frequency of the PWM oscillator.
If this pin is connected to signal ground the internal PWM oscillator is
disabled.
synchronization
input/output
By connecting this pin to the SYNC-pins of other ICs, they can synchronise
their hf-oscillators. Also the IC can synchronise to an external pulse source
connected to this pin.
status signal
input/output
The IC signals a fault condition to an external circuit by pulling this pin low and
external circuits can also signal a fault condition to the IC by pulling this pin
low.
analog PWM dimming The dutycycle of the internally generated PWM signal is proportional to the
input
voltage on this pin.
digital PWM dimming
input/output
Digital output of internally generated PWM signal if a capacitor is connected to
the CPWM-pin.
Digital input of PWM signal if the CPWM-pin is connected to signal ground.
Note that the signal on the PWMd-pin is active low, so low voltage on the
PWMd-pin means lamps are on.
high-side driver output B Gate connection of the high side power switch of full bridge halve B
floating supply output B A buffer capacitor must be connected between this pin and the SHB-pin. This
capacitor is charged when the low side switch B is on and supplies the high
side driver B.
high-side source
connection B
Return for high side gate driver B. Must be connected to the source of the high
side power switch of full bridge halve B.
not connected
HV spacer pin
chip enable input
A low voltage on this pin will reset and shutt down the IC
IC low-voltage supply
input
IC supply
regulated 12 V supply
output/input
A buffer capacitor must be connected between this pin and power ground
low-side driver output B Gate connection of the low side power switch of full bridge halve B
power ground
return for low side drivers A and B
low-side driver output A Gate connection of the low side power switch of full bridge halve A
not connected
HV spacer pin
high-side source
connection A
Return for high side gate driver A. Must be connected to the source of the high
side power switch of full bridge halve A.
floating supply output A A buffer capacitor must be connected between this pin and the SHA-pin. This
capacitor is charged when the low side switch A is on and supplies the high
side driver A.
high-side driver output A Gate connection of the high side power switch of full bridge halve A
UBA2074(A)
Preliminary data sheet
Rev. 02.0 — February 2007
© NXP B.V. 2007. All rights reserved.
5 of 33
Free Datasheet http://www.datasheet4u.net/
5 Page 
NXP Semiconductors
UBA2074(A)
High Voltage Full-bridge control IC for CCFL backlighting
7.7 PWM dimming
During the time within a PWM dim cycle that the lamps are off, switches S1 and S2 are
opened (non-conducting). In this way the regulation level is stored in C1 when the current
regulation loop is opened (see Figure 9).
After the regulation loop is opened, C2 is discharged (the voltage on the CSWP-pin is
swept down) to switch off the lamps, and charged again to turn the lamps on again. The
lamps on versus off time is determined by the signal on the PWMd-pin (low = lamps on).
The minimum phase difference between the bridge halves during the lamps off period of
each PWM cycle is ∆φ(min,lv) in low voltage configuration and ∆φ(min,hv) in high voltage
configuration. ∆φ(min,hv)>∆φ(min,lv) because of the need to keep commuttation current for
zero voltage switching at high bridge voltages.
During the PWM lamps off period the phase shift level at which the lamp current was in
regulation is preserved in the capacitor connected to the CIFB-pin (C1 in Figure 9).
Switches S1 and S2 are closed (conducting) again when the voltage on the CSWP-pin
has reached the voltage on the CIFB-pin again.
The phase shift sweep speed is determined by the capacitor connected to the CSWP-pin
(C2 in Figure 9). The real lamp light output will be slightly less then the PWMd signal duty
cycle because of the phase shift sweep time (see Figure 10). When the lamp-on time is
too short to sweep up the voltage on the CSWP-pin, the IC will wait until the CSWP
voltage has actually reached the current control level before sweeping down again. This
prevents that the lamps go out completely when deep dimming is combined with a too
large capacitor at the CSWP-pin.
Fig 10. Light output as function of PWMa input voltage
Three pins are available to configure the internal PWM generator: the CPWM-, PWMa-,
and the PWMD-pin. The two possible PWM configurations are shown in Figure 11. In the
analog or master mode the internal PWM generator is active and generating the PWM
signal. This signal is put on the PWMd-pin, which is automatically configured as an output.
The minimum dutycycle of the internal PWM generator is limited to DPWM(min,intern).
When the CPWM-pin is connected to ground, the IC is put in digital or slave mode. The
PWMd-pin is then an input and the IC uses the PWM signal provided on the PWMd-pin.
UBA2074(A)
Preliminary data sheet
Rev. 02.0 — February 2007
© NXP B.V. 2007. All rights reserved.
11 of 33
Free Datasheet http://www.datasheet4u.net/
11 Page | ||
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| PDF Descargar | [ Datasheet UBA2074.PDF ] | |
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