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PDF LM98513 Data sheet ( Hoja de datos )
| Número de pieza | LM98513 | |
| Descripción | 50 MSPS Copier Signal Processor | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Rev 3.3 March 2005
LM98513 Dual-Channel, 10-Bit, 50 MSPS Copier Signal Processor
General Description
The LM98513 is a fully integrated, high performance 10-Bit, 50
MSPS CCD signal processing solution for digital copiers and
scanners. High-speed signal throughput is achieved with an
innovative 2-channel architecture including sample and hold,
programmable gain and offset correction and analog-to-digital
conversion. The fully differential processing channels show
exceptional noise immunity, having a very low noise floor of -
68dB each. The fast, temperature stable, 8 bit programmable
gain amplifiers are linear-in-dB which enables fine adjustments
to the signal gain and minimizes cross-channel gain error
caused by mismatch in the CCD output circuitry. The
independently controlled offset correction circuits utilize 8-bit
offset DACs to correct signal and cross-channel offsets. The 10-
bit analog-to-digital converters have excellent dynamic
performance making the LM98513 transparent in the image
reproduction chain.
Applications
Digital Plain Paper Copiers
Multi-Function Printers
Facsimile Equipment
Desktop Publishing
Flatbed or Handheld Color Scanners
High-speed Document Scanner
Features
3 Volt Single Power Supply
Low Power CMOS Design
4 Wire Serial Interface
2.5 Volt Data Output Levels
Dual Inputs with Symmetrical Architecture
Even/Odd Channel Offset Correction
Digital Black Level Clamp
Programmable Input Clamp
Key Specifications
Maximum Input Level
Input Sampling Rate
PGA Gain Steps
PGA Gain Range
ADC Resolution
ADC Sampling Rate
Noise Floor
0.0 dB Gain,1.5 Volt input
Power Dissipation
AV+=DV+=DV+I/O=3.0V
1.5 Volt peak-peak
25 MSPS
256 Steps
0.0 - 20.0 dB
10-Bit
25 MSPS
-68dB
415 mW (typical)
Operating Temp
0 to 70oC
System Block Diagram
CCD/CIS Sensor
LM98513
10
Imager Processor
Sensor Drivers
©2005 National Semiconductor Corporation
Timing Generator
Motor Controllers Microcontroller
www.national.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Pin Name
I/O Typ Res Description
22 VIN ODD I
A
Odd channel analog input signal. AC-couple to imager output through a 0.1µF
capacitor.
23 SDO
OD
Serial interface output port.
24 AGND P Analog ground return.
25 AV+
IP
Power supply for the analog circuits. Bypass supply each supply pin with 0.1µF and
10µF capacitors in parallel.
26 AV+
IP
Power supply for the analog circuits. Bypass supply each supply pin with 0.1µF and
10µF capacitors in parallel.
27 SCLK
ID
Serial interface shift register clock.
28 SHP
D
Clamp override. (Not used in the LM98513) Connect to GND if Analog Input Control
Register bit [0] = 0 (default). Connect to Vdd if bit[0] = 1.
29 CLPIN
I D PD Input Clamp Enable.
30
VREFP
ODD
IO A
Top of odd channel DAC reference ladder. Normally bypassed with a 0.1µF capacitor
to ground. An external DAC reference voltage may be applied to this pin.
31
VREFN
ODD
IO A
Bottom of odd channel DAC reference ladder. Normally bypassed with a 0.1µF
capacitor. An external DAC reference voltage may be applied to this pin.
32
VREFB
ODD
IO A
Bottom of odd channel ADC reference ladder. Normally bypassed with a 0.1µF
capacitor to ground, and a 10µF capacitor to VREFT ODD. An external ADC refer-
ence voltage may be applied to this pin.
33 NC
34 SHD
ID
Sample override. Programmable active-high or active-low through serial interface.
Connect to ground when function not being used (registers values in default condi-
tion).
35 DGND I/O
P
Digital output driver ground return.
36 DV+ I/O
I
P
Power supply for the digital output driver circuits. Bypass supply each supply pin with
0.1µF and 10µF capacitors in parallel.
37 DOUT0
OD
Digital output. Bit 0 of 10 of the digital video output bus.
38 DOUT1
OD
Digital output. Bit 1 of 10 of the digital video output bus.
39 DOUT2
OD
Digital output. Bit 2 of 10 of the digital video output bus.
40 DOUT3
OD
Digital output. Bit 3 of 10 of the digital video output bus.
41 DOUT4
OD
Digital output. Bit 4 of 10 of the digital video output bus.
42 DGND P Digital ground return.
43 DV+
IP
Power supply for the digital circuits. Bypass supply each supply pin with 0.1µF and
10µF capacitors in parallel.
44 DOUT5
OD
Digital output. Bit 5 of 10 of the digital video output bus.
45 DOUT6
OD
Digital output. Bit 6 of 10 of the digital video output bus.
46 DOUT7
OD
Digital output. Bit 7 of 10 of the digital video output bus.
47 DOUT8
OD
Digital output. Bit 8 of 10 of the digital video output bus.
48 DOUT9
OD
Digital output. Bit 9 of 10 of the digital video output bus.
©2005 National Semiconductor Corporation
5
www.national.com
Free Datasheet http://www.datasheet4u.com/
5 Page 
Input Sampling Timing
VIN
SHD1
SAMPLE2
MCLK
tAD
tSHD
1SHD may override the SAMPLE signal’s falling (and rising) edge(s) for sampling the video signal (SHD is active-low by default).
2The SAMPLE signal is an internal signal derived from MCLK whose falling edge samples the CCD video signal by default.
3Timing shown above is for SHD polarity active-high (Bit [0] in Analog input control register = 1).
Figure 4: Input Sample Timing
Digital Output Timing
tAD
n
EVEN
n+1 n+2
n+7 n+8 n+9
n
ODD
MCLK
OUTPUT
DATA
n+1 n+2
10%
n-7 n-6
n-5 tch
tcl
n+7 n+8 n+9
n-2
tRC
90%
10%
n-1
n tFC
OE
tOD
tOH
tDIS tEN
tVALID
Figure 5: Digital Output Data Timing
©2005 National Semiconductor Corporation
11
www.national.com
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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| PDF Descargar | [ Datasheet LM98513.PDF ] | |
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