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TP80C51BH PDF даташит

Спецификация TP80C51BH изготовлена ​​​​«Intel» и имеет функцию, называемую «(TP8xCx1BH) CMOS Single-Chip 8-Bit Microcontroller».

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Номер произв TP80C51BH
Описание (TP8xCx1BH) CMOS Single-Chip 8-Bit Microcontroller
Производители Intel
логотип Intel логотип 

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TP80C51BH Даташит, Описание, Даташиты
87C51/80C51BH/80C31BH
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial/Express
87C51/80C51BH/80C51BHP/80C31BH
*See Table 1 for Proliferation Options
High Performance CHMOS EPROM
24 MHz Operation
Improved Quick-Pulse Programming
Algorithm
3-Level Program Memory Lock
Boolean Processor
128-Byte Data RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Extended Temperature Range
(-40°C to +85 °C)
5 Interrupt Sources
Programmable Serial Port
TTL- and CMOS-Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
ONCE Mode Facilitates System Testing
Power Control Modes
Idle
Power Down
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH). In
addition the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 128 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on
Intel's reliable CHMOS III-E technology. Being a member of the MCS® 51 controller family, the
87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-for-
pin compatible with the existing MCS 51 controller family of products.
The 80C51BHP is identical to the 80C51BH. When ordering the 80C51BHP, customers must submit the 64
byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code
protection and at the same time allows code verification.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
For the remainder of this document, the 87C51, 80C51BH, and 80C31BH will be referred to as the 87C51/BH,
unless information applies to a specific device.
* Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 2004
July 2004
Order Number: 272335-004









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TP80C51BH Даташит, Описание, Даташиты
87C51/80C51BH/80C31BH
80C31BH
80C51BH
80C51BHP
87C51
Table 1. Proliferation Options
Standard
-1
XX
XX
XX
XX
NOTES:
3.5 MHz to 12 MHz; VCC e 5V g20%
-1 3.5 MHz to 16 MHz; VCC e 5V g20%
-2 0.5 MHz to 12 MHz; VCC e 5V g20%
-24 3.5 MHz to 24 MHz; VCC e 5V g20%
-2
X
X
X
X
-24
X
X
X
X
Figure 1. 87C51/BH Block Diagram
272335 ±1
2
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TP80C51BH Даташит, Описание, Даташиты
87C51/80C51BH/80C31BH
PROCESS INFORMATION
The 87C51-B H is manufactured on the CHMOS III-E
process. Additional process and reliability informa-
tion is available in the Intel® Quality System
Handbook .
PACKAGES
Part
87C51-BH
Package Type
40-Pin Plastic DIP (OTP)
40-Pin CERDIP (EPROM)
44-Pin PLCC (OTP)
44-Pin QFP (OTP)
DIP
272335 – 2
PLCC
272335 – 3
*Do not connect reserved pins.
QFP
Figure 2. Pin Connections
272335 – 4
3
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Номер в каталогеОписаниеПроизводители
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