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даташит 74ACT74P PDF ( Datasheet )

74ACT74P Datasheet Download - Toshiba

Номер произв 74ACT74P
Описание TC74ACT74P
Производители Toshiba
логотип Toshiba логотип 


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74ACT74P Даташит, Описание, Даташиты
TC74ACT74P/F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT74P,TC74ACT74F,TC74ACT74FN,TC74ACT74FT
Dual D-Type Flip Flop with Preset and Clear
The TC74ACT74 is an advanced high speed CMOS D-FLIP
FLOP fabricated with silicon gate and double-layer metal wiring
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CK pulse.
CLR and PR are independent of the CK and are
accomplished by setting the appropriate input to an “L” level.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
High speed: fmax = 180 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
Balanced propagation delays: tpLH ∼− tpHL
Pin and function compatible with 74F74
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74ACT74P
TC74ACT74F
TC74ACT74FN
TC74ACT74FT
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
SOL14-P-150-1.27
TSSOP14-P-0044-0.65A
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.12 g (typ.)
: 0.06 g (typ.)
1 2007-10-01
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74ACT74P Даташит, Описание, Даташиты
Pin Assignment
1CLR 1
1D 2
1CK 3
1PR 4
1Q 5
1Q 6
GND 7
CK D
QQ
CK D
QQ
(top view)
14 VCC
13 2CLR
12 2D
11 2CK
10 2PR
9 2Q
8 2Q
Truth Table
CLR
L
H
L
H
H
H
Inputs
PR D
HX
LX
LX
HL
HH
HX
X: Don’t care
Outputs
CK Q
Q
Function
XLH
Clear
XHL
Preset
XHH
LH
HL
Qn Qn No Change
System Diagram
CLR
PR
1/13
4/10
TC74ACT74P/F/FN/FT
IEC Logic Symbol
1PR
1CK
1D
1CLR
2PR
2CK
2D
2CLR
(4)
(3)
(2)
(1)
(10)
(11)
(12)
(13)
S
C1
1D
R
(5) 1Q
(6) 1Q
(9) 2Q
(8) 2Q
6/8 Q
D 2/12
ϕ
φ
φ
CK 3/11
φ
ϕ
ϕ
5/9 Q
2 2007-10-01
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74ACT74P Даташит, Описание, Даташиты
Absolute Maximum Ratings (Note 1)
TC74ACT74P/F/FN/FT
Characteristics
Symbol
Rating
Unit
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC VCC/ground current
Power dissipation
Storage temperature
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
PD
Tstg
0.5 to 7.0
0.5 to VCC + 0.5
0.5 to VCC + 0.5
±20
±50
±50
±100
500 (DIP) (Note 2)/180 (SOP/TSSOP)
65 to 150
V
V
V
mA
mA
mA
mA
mW
°C
Note 1:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = 40°C to 65°C. From Ta = 65°C to 85°C a derating factor of 10 mW/°C
should be applied up to 300 mW.
Operating Ranges (Note)
Characteristics
Symbol
Rating
Unit
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall time
VCC
VIN
VOUT
Topr
dt/dV
4.5 to 5.5
0 to VCC
0 to VCC
40 to 85
0 to 10
V
V
V
°C
ns/V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
3 2007-10-01
Free Datasheet http://www.datasheet4u.com/








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