No Preview Available !

4Gb DDR3 SDRAM
4Gb DDR3 SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TQ4G83MFR-xxC
H5TQ4G83MFR-xxI
H5TQ4G83MFR-xxJ
H5TQ4G63MFR-xxC
H5TQ4G63MFR-xxI
H5TQ4G63MFR-xxJ
* Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 1.0/ Feb. 2012
1
Free Datasheet http://www.datasheet4u.com/

 
	 
No Preview Available !

Revision History
Revision No.
History
Draft Date
0.1
Initial Release
Apr. 2011
0.2
Ballout typo correction
May. 2011
0.3
Package Dimension correction
Jun. 2011
0.4
Add I-part
July. 2011
0.5
Product type correction
Oct. 2011
0.6
Update operation frequency
Oct. 2011
0.7
Update IDD
Nov. 2011
0.8
Update IDD
Nov. 2011
0.9
Package Ball out (Top View) Correction
Feb. 2012
(X8/16)
Add J-part support
1.0 Pakage Dimension (Botton View) Correction Feb. 2012
(X8/16)
Remark
Page 5 to 6 , Pin Coordination is
changed from 1-11 to 1-9
Page 1 to 3, add H5TQ4G83MFR-xxJ
Page 32 to 33, Pin Coordination is
changed from 1-11 to 1-9
Rev. 1.0/ Feb. 2012
2
Free Datasheet http://www.datasheet4u.com/

 
	 
No Preview Available !

Description
The H5TQ4G83MFR-xxC,H5TQ4G63MFR-xxC, H5TQ4G83MFR-xxI, H5TQ4G63MFR-xxI, H5TQ4G83MFR-xxJ
and H5TQ4G63MFR-xxJ are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM,
ideally suited for the main memory applications which requires large memory density and high bandwidth.
Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of
the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of
the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10 and 11, 13
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase of0 oC~95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
Commercial Temperature( 0oC ~ 85 oC)
Industrial Temperature( -40oC ~ 95 oC)
• Auto Self Refresh supported
• JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
* This product in compliance with the RoHS directive.
Rev. 1.0/ Feb. 2012
3
Free Datasheet http://www.datasheet4u.com/