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PDF 74HC245 Data sheet ( Hoja de datos )

Número de pieza 74HC245
Descripción Octal 3-State Noninverting Bus Transceiver
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74HC245 datasheet


1. Octal Bus Transceiver - NXP






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No Preview Available ! 74HC245 Hoja de datos, Descripción, Manual

74HC245
Octal 3−State Noninverting
Bus Transceiver
HighPerformance SiliconGate CMOS
The 74HC245 is identical in pinout to the LS245. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC245 is a 3state noninverting transceiver that is used for
2way asynchronous communication between data buses. The device
has an activelow Output Enable pin, which is used to place the I/O
ports into highimpedance states. The Direction control determines
whether data flows from A to B or from B to A.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 308 FETs or 77 Equivalent Gates
This is a PbFree Device
http://onsemi.com
MARKING
DIAGRAMS
20
1
20
TSSOP20
DT SUFFIX
CASE 948E
1
HC
245
ALYW G
G
HC245
A
L
Y
W
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 Rev. 1
1
Publication Order Number:
74HC245/D
Free Datasheet http://www.datasheet4u.com/

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74HC245 pdf
74HC245
INPUT
A OR B
tr
tPLH
OUTPUT
B OR A
5900%%
10%
90%
50%
10%
tTLH
DIRECTION
tf
VCC
GND
tPHL
OUTPUT
ENABLE
A OR B
tTHL
A OR B
Figure 3. Switching Waveform
50%
tPZL tPLZ
50%
tPZH
50%
tPHZ
50%
10%
90%
VCC
GND
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
Figure 4. Switching Waveform
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
DEVICE
UNDER
TEST
TEST POINT
OUTPUT 1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6. Test Circuit
http://onsemi.com
5
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