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MPC8245 PDF даташит
| Спецификация MPC8245 изготовлена «Freescale» и имеет функцию, называемую «Integrated Processor». |
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Детали детали
| Номер произв | MPC8245 |
| Описание | Integrated Processor |
| Производители | Freescale |
| логотип |  |
30 Pages
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Freescale Semiconductor
Technical Data
MPC8245EC
Rev. 10, 08/2007
MPC8245 Integrated Processor
Hardware Specifications
The MPC8245 combines a PowerPC™ MPC603e processor
core built on Power Architecture™ technology with a PCI
bridge so that system designers can rapidly design systems
using peripherals designed for PCI and the other standard
interfaces. Also, a high-performance memory controller
supports various types of ROM and SDRAM. The MPC8245
is the second of a family of products that provide
system-level support for industry-standard interfaces with an
MPC603e processor core.
This hardware specification describes pertinent electrical
and physical characteristics of the MPC8245. For functional
characteristics of the processor, refer to the MPC8245
Integrated Processor Reference Manual (MPC8245UM).
For published errata or updates to this document, visit the
website listed on the back cover of the document.
1 Overview
The MPC8245 integrated processor is composed of a
peripheral logic block and a 32-bit superscalar MPC603e
core, as shown in Figure 1.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Electrical and Thermal Characteristics . . . . . . . . . . . . 5
5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 31
6. PLL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8. Document Revision History . . . . . . . . . . . . . . . . . . . 56
9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 62
© Freescale Semiconductor, Inc., 2001–2007. All rights reserved.
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Overview
MPC8245
Additional Features:
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
Processor Core Block
(64-Bit) Two-Instruction Fetch
Processor
PLL
Branch
Processing
Unit
Instruction Unit
(BPU)
(64-Bit) Two-Instruction Dispatch
System
Register
Unit
(SRU)
Integer
Unit
(IU)
Load/Store
Unit
(LSU)
Floating-
Point
Unit
(FPU)
Data
MMU
16-Kbyte
Data
Cache
64-Bit
Instruction
MMU
16-Kbyte
Instruction
Cache
Peripheral Logic Bus
I2C
5 IRQs/
16 Serial
Interrupts
Peripheral Logic Block
Message
Unit
(with I2O)
DMA
Controller
Address
(32-Bit)
Data (64-Bit)
Central
Control
Unit
Data Path
ECC Controller
Memory
Controller
I2C
Controller
Performance
Monitor
DLL
PIC
Interrupt
Controller/
Timers
Peripheral Logic
PLL
Configuration
Registers
Data Bus
(32- or 64-Bit)
with 8-Bit Parity
or ECC
Memory/ROM/
PortX Control/Address
SDRAM_SYNC_IN
SDRAM Clocks
PCI_SYNC_IN
DUART
PCI Bus
Interface Unit
Watchpoint
Facility
Address
PCI
Translator Arbiter
Fanout PCI Bus
Buffers Clocks
32-Bit
Five
PCI Interface Request/Grant Pairs
Figure 1. MPC8245 Block Diagram
OSC_IN
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
2 Freescale Semiconductor
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Features
The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),
memory controller,
I2C controller. The
DMA controller,
processor core is
PIC interrupt controller, a message unit (and I2O
a full-featured, high-performance processor with
interface), and
floating-point
an
support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and power
management features. The integration reduces the overall packaging requirements and the number of
discrete devices required for an embedded system.
An internal peripheral logic bus interfaces the processor core to the peripheral logic. The core can operate
at a variety of frequencies, allowing the designer to trade off performance for power consumption. The
processor core is clocked from a separate PLL that is referenced to the peripheral logic PLL. This allows
the microprocessor and the peripheral logic block to operate at different frequencies while maintaining a
synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus
width) and a 32-bit address bus along with control signals that enable the interface between the processor
and peripheral logic to be optimized for performance. PCI accesses to the MPC8245 memory space are
passed to the processor bus for snooping when snoop mode is enabled.
The general-purpose processor core and peripheral logic serve a variety of embedded applications. The
MPC8245 can be used as either a PCI host or PCI agent controller.
2 Features
Major features of the MPC8245 are as follows:
• Processor core
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—Entire cache or on a per-way basis up to three of four ways
— Dynamic power management: 60x nap, doze, and sleep modes
• Peripheral logic
— Peripheral logic bus
– Various operating frequencies and bus divider ratios
– 32-bit address bus, 64-bit data bus
– Full memory coherency
– Decoupled address and data buses for pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI writes
— Memory interface
– Up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRAM
– Programmable timing supporting SDRAM
– One to eight banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
3
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