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MPC8240EC PDF даташит
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Детали детали
| Номер произв | MPC8240EC |
| Описание | microprocessor |
| Производители | Motorola Semiconductors |
| логотип |  |
30 Pages
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Advance Information
MPC8240EC
Rev. 4, 11/2003
MPC8240
Integrated Processor
Hardware Specifications
Freescale Semiconductor, Inc.
The MPC8240 combines a MPC603e core microprocessor with a PCI bridge. The MPC8240
PCI support allows system designers to rapidly create systems using peripherals already
designed for PCI and the other standard interfaces. The MPC8240 also integrates a
high-performance memory controller that supports various types of DRAM and ROM. The
MPC8240 is the first of a family of products that provide system-level support for industry
standard interfaces with PowerPC™ microprocessor cores.
This hardware specification describes pertinent electrical and physical characteristics of the
MPC8240. For functional characteristics of the processor, refer to the MPC8240 Integrated
Processor User’s Manual (MPC8240UM).
This hardware specification contains the following topics:
Topic
Section 1.1, “Overview”
Section 1.2, “Features”
Section 1.3, “General Parameters”
Section 1.4, “Electrical and Thermal Characteristics”
Section 1.5, “Package Description”
Section 1.6, “PLL Configurations”
Section 1.7, “System Design Information”
Section 1.8, “Document Revision History”
Section 1.9, “Ordering Information”
Page
1
3
5
5
27
34
35
45
49
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors.
1.1 Overview
The MPC8240 integrated processor is comprised of a peripheral logic block and a 32-bit
superscalar MPC603e core, as shown in Figure 1.
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Overview
Freescale Semiconductor, Inc.
MPC8240
Additional Features:
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
Processor Core Block
(64-Bit) Two-Instruction Fetch
Processor
PLL
Branch
Processing
Unit
Instruction Unit
(BPU)
(64-Bit) Two-Instruction Dispatch
System
Register
Unit
(SRU)
Integer
Unit
(IU)
Load/Store
Unit
(LSU)
Floating-
Point
Unit
(FPU)
Data
MMU
16-Kbyte
Data
Cache
64-Bit
Instruction
MMU
16-Kbyte
Instruction
Cache
Peripheral Logic Bus
I2C
5 IRQs/
16 Serial
Interrupts
Peripheral Logic Block
Message
Unit
(with I2O)
DMA
Controller
I2C
Controller
PIC
Interrupt
Controller/
Timers
Address
(32-Bit)
Data (64-Bit)
Data Path
ECC Controller
Central
Control
Unit
Memory
Controller
Configuration
Registers
DLL
PCI Bus
Interface Unit
Address
PCI
Translator Arbiter
Peripheral Logic
PLL
Fanout
Buffers
Data Bus
(32- or 64-Bit)
with 8-Bit Parity
or ECC
Address/Control
DRAM/SDRAM/
ROM/Flash/Port X
SDRAM Sync In
SDRAM Sync Out
SDRAM Clocks
PCI Clock In
PCI Bus Clocks
32-Bit
Five
PCI Interface Request/Grant
Pairs
Figure 1. MPC8240 Block Diagram
OSC In
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, PIC interrupt controller,
I2O controller, and an I2C controller. The MPC603e core is a full-featured, high-performance processor with
floating-point support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and
2
MPC8240 Integrated Processor Hardware Specifications
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Free Datasheet http://www.datasheet4u.com/
No Preview Available ! |
Freescale Semiconductor, Inc.
Features
power management features. The integration reduces the overall packaging requirements and the number of
discrete devices required for an embedded system.
The MPC8240 contains an internal peripheral logic bus that interfaces the MPC603e core to the peripheral
logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for
power consumption. The MPC603e core is clocked from a separate PLL, which is referenced to the
peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different
frequencies while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus
(depending on memory data bus width) and a 32-bit address bus along with control signals that enable the
interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the
MPC8240 memory space are passed to the processor bus for snooping purposes when snoop mode is
enabled.
The MPC8240 features serve a variety of embedded applications. In this way, the MPC603e core and
peripheral logic remain general-purpose. The MPC8240 can be used as either a PCI host or an agent
controller.
1.2 Features
This section summarizes features of the MPC8240. Major features of the MPC8240 are as follows:
• Peripheral logic
— Memory interface
– Programmable timing supporting either FPM DRAM, EDO DRAM, or SDRAM
– High-bandwidth bus (32- or 64-bit data bus) to DRAM
– Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices
– Supports 1-Mbyte to 1-Gbyte DRAM memory
– 16 Mbytes of ROM space
– 8-, 32-, or 64-bit ROM
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
– Low-voltage TTL logic (LVTTL) interfaces
– Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing
— 32-bit PCI interface operating up to 66 MHz
– PCI 2.1-compliant
– PCI 5.0-V tolerance
– Support for PCI locked accesses to memory
– Support for accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
MOTOROLA
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
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| Номер в каталоге | Описание | Производители |
| MPC8240EC | microprocessor | Motorola Semiconductors |
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