ADRF6850 PDF даташит

Спецификация ADRF6850 изготовлена «Analog Devices» и имеет функцию, называемую «100 MHz to 1000 MHz Integrated Broadband Receiver».

Детали детали

Номер произв	ADRF6850
Описание	100 MHz to 1000 MHz Integrated Broadband Receiver
Производители	Analog Devices
логотип

30 Pages

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FEATURES

IQ quadrature demodulator

Integrated fractional-N PLL and VCO

Gain control range: 60 dB

Input frequency range: 100 MHz to 1000 MHz

Input P1dB: +12 dBm at 0 dB gain

Input IP3: +22.5 dBm at 0 dB gain

Noise figure: 11 dB at >39 dB gain, 49 dB at 0 dB gain

Baseband 1 dB bandwidth: 250 MHz in wideband mode,

50 MHz in narrow-band mode

SPI/I2C serial interface

Power supply: +3.3 V/350 mA

APPLICATIONS

Broadband communications

Cellular communications

Satellite communications

100 MHz to 1000 MHz

Integrated Broadband Receiver

ADRF6850

GENERAL DESCRIPTION

The ADRF6850 is a highly integrated broadband quadrature

demodulator, frequency synthesizer, and variable gain amplifier

(VGA). The device covers an operating frequency range from

100 MHz to 1000 MHz for use in both narrow-band and wideband

communications applications, performing quadrature demodu-

lation from IF directly to baseband frequencies.

The ADRF6850 demodulator includes a high modulus

fractional-N frequency synthesizer with integrated VCO,

providing better than 1 Hz frequency resolution, and a 60 dB

gain control range provided by a front-end VGA.

Control of all the on-chip registers is through a user-selected

SPI interface or I2C interface. The device operates from a single

power supply ranging from 3.15 V to 3.45 V.

VCC1

VCC2

VCC3

FUNCTIONAL BLOCK DIAGRAM

VCC4 VCC5 VCC6 VCC7 VCC8 VCC9

LOMON LOMON

60dB

GAIN CONTROL

RANGE

RFI

RFCM

VGAIN

SEQUENCED

GAIN

INTERFACE

0°/90°

DRIVER

RFDIV

VCO

CORE

REFIN

×2

DOUBLER

SDI/SDA

CLK/SCL

SDO

SPI/

I2C

INTERFACE

ADRF6850

5-BIT

DIVIDER

÷2

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

+ PHASE

FREQUENCY

– DETECTOR

REFERENCE

CHARGE

PUMP

N-COUNTER

CURRENT SETTING

RFCP4 RFCP3 RFCP2 RFCP1

FRACTIONAL MODULUS

225

INTEGER

GND

MUXOUT

Figure 1.

IBB

CCOMP1

CCOMP2

CCOMP3

VTUNE

VOCM

QBB

RSET

LF3

LF2

LDET

TESTLO

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

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ADRF6850

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 18

Overview...................................................................................... 18

PLL Synthesizer and VCO......................................................... 18

Quadrature Demodulator.......................................................... 20

Variable Gain Amplifier (VGA) ............................................... 20

REVISION HISTORY

10/10—Revision 0: Initial Version

I2C Interface ................................................................................ 20

SPI Interface ................................................................................ 22

Program Modes .......................................................................... 24

Suggested Power-Up Sequence..................................................... 30

Initial Register Write Sequence ................................................ 30

Evaluation Board ............................................................................ 31

General Description................................................................... 31

Hardware Description ............................................................... 31

PCB Schematic............................................................................ 33

PCB Artwork............................................................................... 34

Bill of Materials........................................................................... 35

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

Rev. 0 | Page 2 of 36

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ADRF6850

SPECIFICATIONS

VCC = 3.3 V; ambient temperature (TA) = 25°C; ZS = 50 Ω; ZL = 100 Ω differential; PLL loop bandwidth = 50 kHz; REFIN = 13.5 MHz;

PFD = 27 MHz; baseband frequency = 20 MHz, narrow-band mode, unless otherwise noted.

Table 1.

Parameter

RF INPUT

Operating Frequency Range

Input P1dB

Input IP3

Input IP2

Noise Figure (NF)

Maximum Gain

Minimum Gain

Gain Conformance Error1

Gain Slope

VGAIN Input Impedance

Return Loss

REFERENCE CHARACTERISTICS

Input Frequency

REFIN Input Sensitivity

REFIN Input Capacitance

REFIN Input Current

CHARGE PUMP

ICP Sink/Source

High Value

Low Value

Absolute Accuracy

VCO

Gain

SYNTHESIZER SPECIFICATIONS

Frequency Increment

Phase Frequency Detector

Spurs

Phase Noise

Integrated Phase Noise

Test Conditions/Comments

RFI, RFI, VGAIN pins

0 dB gain

60 dB gain

0 dB gain

60 dB gain

0 dB gain, single-ended input

60 dB gain, single-ended input

0 dB gain

<39 dB gain NF rises 1:1 as gain in dB falls

>39 dB gain

ZS = 50 Ω single-ended, ZL = 100 Ω differential

VGAIN from 200 mV to 1.3 V

Relative to ZS = 50 Ω, 100 MHz to 1 GHz

REFIN pin

With R divide-by-2 divider enabled

With R divide-by-2 divider disabled

CP and RSET pins

Programmable

With RSET = 4.7 kΩ

KVCO

Loop bandwidth = 50 kHz

Integer boundary < loop bandwidth

>10 MHz offset from carrier

LO frequency = 1000 MHz

@ 10 Hz offset

@ 100 Hz offset

@ 1 kHz offset

@ 10 kHz offset

@ 100 kHz offset

@ 1 MHz offset

>10 MHz offset

1 kHz to 8 MHz integration bandwidth

Min Typ Max Unit

100 1000 MHz

+12 dBm

−48 dBm

+22.5

dBm

−38 dBm

+40 dBm

−20 dBm

49 dB

11 dB

60 dB

0 dB

0.5 dB

25 mV/dB

20 kΩ

15 dB

10 300 MHz

10 165 MHz

0.4 VCC V p-p

10 pF

±100 µA

312.5

2.5

µA

15 MHz/V

30 MHz

−55 dBc

−70 dBc

−75

−80

−90

−98

−110

−136

−149

0.26

dBc/Hz

°rms

Rev. 0 | Page 3 of 36

Free Datasheet http://www.datasheet4u.com/

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Номер в каталоге	Описание	Производители
ADRF6850	100 MHz to 1000 MHz Integrated Broadband Receiver	Analog Devices

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