|
ADRF6807 PDF даташит
| Спецификация ADRF6807 изготовлена «Analog Devices» и имеет функцию, называемую «700 MHz to 1050 MHz Quadrature Demodulator». |
|
|
Детали детали
| Номер произв | ADRF6807 |
| Описание | 700 MHz to 1050 MHz Quadrature Demodulator |
| Производители | Analog Devices |
| логотип |  |
36 Pages
No Preview Available ! |
Data Sheet
700 MHz to 1050 MHz Quadrature
Demodulator with Fractional-N PLL
ADRF6807
FEATURES
GENERAL DESCRIPTION
IQ demodulator with integrated fractional-N PLL
LO frequency range: 700 MHz to 1050 MHz
For the following specifications (LPEN = 0)/(LPEN = 1):
Input P1dB: 12.8 dBm/11.7 dBm
Input IP3: 26.7 dBm/24.0 dBm
Noise figure (DSB): 13.1 dB/12.4 dB
Voltage conversion gain: 1.0 dB/4.3 dB
Quadrature demodulation accuracy
Phase accuracy: <0.5°
Amplitude accuracy: <0.1 dB
Baseband demodulation: 170 MHz/135 MHz, 3 dB
bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
The ADRF6807 is a high dynamic range IQ demodulator with
integrated phase-locked loop (PLL) and voltage controlled
oscillator (VCO). The fractional-N PLL/synthesizer generates a
frequency in the range of 2.8 GHz to 4.2 GHz. A programmable
quadrature divider (divide ratio = 4) divides the output frequency
of the VCO down to the required local oscillator (LO) frequency to
drive the mixers in quadrature. Additionally, an output divider
(divide ratio = 4 to 8) generates a divided-down VCO signal for
external use.
The PLL reference input is supported from 9 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
A reduced power mode of operation is also provided by
programming the serial interface registers to reduce current
consumption, with slightly degraded input linearity and output
current drive.
The ADRF6807 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
LON 37
LOP 38
GND 11
DATA 12
CLK 13
LE 14
GND 15
REFIN 6
GND 7
MUXOUT 8
GND VCCLO VCCLO
35 34
17
FUNCTIONAL BLOCK DIAGRAM
LOSEL
36
BUFFER
CTRL
BUFFER
DIV
÷4,
÷6,
÷8
ADRF6807
FRACTION
REG
MODULUS
INTEGER
REG
BUFFER
MUX
DIVIDER
÷2
IBBP
33
IBBN GND
32 31
30 GND
29 DECL3
28 VCCRF
27 GND
SPI
INTERFACE
×2
MUX
÷2
÷4
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
PRESCALER
÷2
VCO
CORE
QUAD
÷2
26 RFIN
25 RFIP
TEMP
SENSOR
–
+
PHASE
FREQUENCY
DETECTOR
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2.5V LDO
VCO LDO
24 GND
23 VOCM
22 VCCBB
21 GND
1
VCC1
2
VCC1
34
5
9 10 39
40
16
CPOUT GND RSET DECL2 VCC2 VTUNE DECL1 GND
18 19 20
QBBP QBBN GND
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
No Preview Available ! |
ADRF6807
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Synthesizer/PLL .......................................................................... 12
Complementary Cumulative Distribution Functions
(CCDF) ........................................................................................ 13
Circuit Description......................................................................... 14
LO Quadrature Drive................................................................. 14
V-to-I Converter......................................................................... 14
Mixers .......................................................................................... 14
Emitter Follower Buffers ........................................................... 14
Bias Circuitry .............................................................................. 14
REVISION HISTORY
2/12—Rev. A to Rev. B
Changes to Table 1............................................................................ 3
Changes to Figure 21 and to Changes to Figure 24 Through
Figure 26 .......................................................................................... 12
Changes to Figure 34...................................................................... 16
Changes to Figure 37...................................................................... 18
Changes to Figure 38...................................................................... 19
Changes to Figure 39...................................................................... 20
Changes to EVM Measurements Section and Changes to
Figure 42 .......................................................................................... 24
Changes to Figure 43...................................................................... 25
Added Figure 44; Renumbered Sequentially .............................. 26
Changes to Figure 45 and Figure 46............................................. 27
Changes to Table 7.......................................................................... 29
Changes to Figure 47...................................................................... 30
Changes to Figure 48...................................................................... 31
9/11—Rev. 0 to Rev. A
Changes to EVM Measurements Section and Figure 42 ........... 24
8/11—Revision 0: Initial Version
Data Sheet
Register Structure....................................................................... 14
LO Divider Programming......................................................... 21
Programming Example.............................................................. 21
Applications Information .............................................................. 22
Basic Connections...................................................................... 22
Supply Connections ................................................................... 22
Synthesizer Connections ........................................................... 22
I/Q Output Connections ........................................................... 23
RF Input Connections ............................................................... 23
Charge Pump/VTUNE Connections ...................................... 23
LO Select Interface ..................................................................... 23
External LO Interface ................................................................ 23
Setting the Frequency of the PLL ............................................. 23
Register Programming............................................................... 23
EVM Measurements .................................................................. 24
Evaluation Board Layout and Thermal Grounding................... 25
ADRF6807 Software .................................................................. 30
Characterization Setups................................................................. 32
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
Rev. B | Page 2 of 36
Free Datasheet http://www.datasheet4u.com/
No Preview Available ! |
Data Sheet
ADRF6807
SPECIFICATIONS
VS1 (VVCCBB and VVCCRF) = 5 V, and VS2 (VVCC1, VVCC2, and VVCCLO) = 3.3 V; ambient temperature (TA) = 25°C; fREF = 26 MHz, fLO = 900 MHz,
fBB = 4.5 MHz, RLOAD = 450 Ω differential, RF port driven from a 1:2 balun to step up the 50 Ω source impedance to match the 100 Ω
differential RF input port impedance, all register and PLL settings use the recommended values shown in the Register Structure section,
unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
RF INPUT at 900 MHz
Input Return Loss
Input P1dB
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
Noise Figure
LO-to-RF Leakage
I/Q BASEBAND OUTPUTS
Voltage Conversion Gain
Demodulation Bandwidth
Quadrature Phase Error
I/Q Amplitude Imbalance
Output DC Offset (Differential)
Output Common-Mode Reference
Common-Mode Offset
Gain Flatness
Maximum Output Swing
Maximum Output Current
LO INPUT/OUTPUT
Output Level (LPEN = 0)
Output Level (LPEN = 1)
Input Level
Input Impedance
LO Main Divider
VCO Output Divider Range
VCO Operating Frequency
Test Conditions/Comments
RFIP, RFIN pins
Relative to 100 Ω
LPEN = 0 (standard power mode)
LPEN = 1 (low power mode)
LPEN = 0; −5 dBm each tone
LPEN = 1; −5 dBm each tone
LPEN = 0; −5 dBm each tone
LPEN = 1; −5 dBm each tone
Double sideband from RF to either I or Q output; LPEN = 0
Double sideband from RF to either I or Q output; LPEN = 1
With a −5 dBm interferer 5 MHz away
At 1×LO frequency, 100 Ω termination at the RF port
IBBP, IBBN, QBBP, QBBN pins
450 Ω differential load across IBBP, IBBN (or QBBP, QBBN);
LPEN = 0
450 Ω differential load across IBBP, IBBN (or QBBP, QBBN);
LPEN = 1
1 V p-p signal 3 dB bandwidth; LPEN = 0
1 V p-p signal 3 dB bandwidth; LPEN = 1
VOCM applied input voltage
|(VIBBP + VIBBN)/2 − VVOCM|, |(VQBBP + VQBBN)/2 − VVOCM|
Any 5 MHz
Differential 450 Ω load
Differential 200 Ω load
Each pin
LOP, LON
Into a differential 50 Ω load, LO buffer enabled (output
frequency = 800 MHz)
Into a differential 50 Ω load, LO buffer enabled (output
frequency = 800 MHz)
Externally applied 2×LO, PLL disabled
Externally applied 2×LO, PLL disabled
VCO to mixer, including quadrature divider, see Table 5 for
divider programming
VCO to (LOP, LON), see Table 6 for supported output divider
modes
Min Typ
700
Max Unit
1050 MHz
−18 dB
12.8 dBm
11.7 dBm
>65 dBm
>65 dBm
26.7 dBm
24.0 dBm
13.1 dB
12.4 dB
16 dB
−73 dBm
1
4.3
170
135
0.35
0.05
±8
1.55 1.65
25
0.2
3
2.4
6
dB
dB
MHz
MHz
Degrees
dB
mV
1.75 V
mV
dB p-p
V p-p
V p-p
mA p-p
1 dBm
−0.75
dBm
0 dBm
50 Ω
4
48
2800
4200 MHz
Rev. B | Page 3 of 36
Free Datasheet http://www.datasheet4u.com/
Скачать PDF:
[ ADRF6807.PDF Даташит ]
| Номер в каталоге | Описание | Производители |
| ADRF6801 | 750 MHz to 1150 MHz Quadrature Demodulator | Analog Devices |
| ADRF6806 | 50 MHz to 525 MHz Quadrature Demodulator | Analog Devices |
| ADRF6807 | 700 MHz to 1050 MHz Quadrature Demodulator | Analog Devices |
| Номер в каталоге | Описание | Производители |
| TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
 Unisonic Technologies |
| IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
 Vishay |
| LM317 | Линейный стабилизатор напряжения, 1,5 А |
 STMicroelectronics |
|
DataSheet26.com | 2020 | Контакты | Поиск |