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Спецификация AD9639 изготовлена «Analog Devices» и имеет функцию, называемую «170 MSPS/210 MSPS Serial Output 1.8 V ADC».

Детали детали

Номер произв	AD9639
Описание	170 MSPS/210 MSPS Serial Output 1.8 V ADC
Производители	Analog Devices
логотип

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Data Sheet

Quad, 12-Bit, 170 MSPS/210 MSPS

Serial Output 1.8 V ADC

AD9639

FEATURES

4 ADCs in one package

JESD204 coded serial digital outputs

On-chip temperature sensor

−95 dB channel-to-channel crosstalk

SNR: 65 dBFS with AIN = 85 MHz at 210 MSPS

SFDR: 77 dBc with AIN = 85 MHz at 210 MSPS

Excellent linearity

DNL: ±0.28 LSB (typical)

INL: ±0.7 LSB (typical)

780 MHz full power analog bandwidth

Power dissipation: 325 mW per channel at 210 MSPS

1.25 V p-p input voltage range, adjustable up to 1.5 V p-p

1.8 V supply operation

Clock duty cycle stabilizer

Serial port interface features

Power-down modes

Digital test pattern enable

Programmable header

Programmable pin functions (PGMx, PDWN)

APPLICATIONS

Communication receivers

Cable head end equipment/M-CMTS

Broadband radios

Wireless infrastructure transceivers

Radar/military-aerospace subsystems

Test equipment

GENERAL DESCRIPTION

The AD9639 is a quad, 12-bit, 210 MSPS analog-to-digital con-

verter (ADC) with an on-chip temperature sensor and a high

speed serial interface. It is designed to support the digitizing

of high frequency, wide dynamic range signals with an input

bandwidth of up to 780 MHz. The output data is serialized

and presented in packet format, consisting of channel-specific

information, coded samples, and error code correction.

The ADC requires a single 1.8 V power supply. The input clock

can be driven differentially with a sine wave, LVPECL, CMOS,

or LVDS. A clock duty cycle stabilizer allows high performance

at full speed with a wide range of clock duty cycles. The on-chip

reference eliminates the need for external decoupling and can

be adjusted by means of SPI control.

Various power-down and standby modes are supported. The

ADC typically consumes 150 mW per channel with the digital

link still in operation when standby operation is enabled.

FUNCTIONAL BLOCK DIAGRAM

AVDD

PDWN

DRVDD DRGND

VIN + A

VIN – A

VCM A

VIN + B

VIN – B

VCM B

VIN + C

VIN – C

VCM C

VIN + D

VIN – D

VCM D

RBIAS

TEMPOUT

AD9639

BUF SHA

PIPELINE

ADC

DOUT + A

CHANNEL A

DOUT – A

BUF SHA

PIPELINE

ADC

DOUT + B

CHANNEL B

DOUT – B

BUF SHA

PIPELINE

ADC

DOUT + C

CHANNEL C

DOUT – C

BUF SHA

PIPELINE

ADC

DOUT + D

CHANNEL D

DOUT – D

REFERENCE

SERIAL

PORT

DATA RATE

MULTIPLIER

PGM3

PGM2

PGM1

PGM0

RESET

SCLK SDI/ SDO CSB CLK+ CLK–

SDIO

Figure 1.

Fabricated on an advanced CMOS process, the AD9639 is avail-

able in a Pb-free/RoHS-compliant, 72-lead LFCSP package. It is

specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Four ADCs are contained in a small, space-saving package.

2. An on-chip PLL allows users to provide a single ADC

sampling clock; the PLL distributes and multiplies up to

produce the corresponding data rate clock.

3. The JESD204 coded data rate supports up to 4.2 Gbps

per channel.

4. The AD9639 operates from a single 1.8 V power supply.

5. Flexible synchronization schemes and programmable

mode pins are available.

6. An on-chip temperature sensor is included.

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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AD9639

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagram ........................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Equivalent Circuits ......................................................................... 15

REVISION HISTORY

7/13—Rev. A to Rev. B

Change to Current Drive Parameter, Table 1................................ 3

Updated Outline Dimensions ....................................................... 36

2/10—Rev. 0 to Rev. A

Changes to Differential Input Voltage Range Parameter,

Table 1 ................................................................................................ 3

Changes to Table 7............................................................................ 9

Changes to Digital Outputs and Timing Section ....................... 25

Change to Addr. (Hex) 0x01, Table 15......................................... 32

5/09—Revision 0: Initial Version

Data Sheet

Theory of Operation ...................................................................... 17

Analog Input Considerations ................................................... 17

Clock Input Considerations...................................................... 19

Digital Outputs ........................................................................... 21

Serial Port Interface (SPI).............................................................. 29

Hardware Interface..................................................................... 29

Memory Map .................................................................................. 31

Reading the Memory Map Table.............................................. 31

Reserved Locations .................................................................... 31

Default Values ............................................................................. 31

Logic Levels................................................................................. 31

Applications Information .............................................................. 35

Power and Ground Recommendations ................................... 35

Exposed Paddle Thermal Heat Slug Recommendations ...... 35

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

Rev. B | Page 2 of 36

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Data Sheet

AD9639

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless

otherwise noted.

Table 1.

Parameter1

RESOLUTION

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error

Gain Matching

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

ANALOG INPUTS

Differential Input Voltage Range2

Common-Mode Voltage

Input Capacitance

Input Resistance

Analog Bandwidth, Full Power

Voltage Common Mode (VCM x Pins)

Voltage Output

Current Drive

TEMPERATURE SENSOR OUTPUT

Voltage Output

Current Drive

POWER SUPPLY

AVDD

DRVDD

IAVDD

IDRVDD

Total Power Dissipation

(Including Output Drivers)

Power-Down Dissipation

Standby Dissipation2

CROSSTALK

Overrange Condition3

Temp

Full

25°C

Full

25°C

Full

AD9639BCPZ-170

Min Typ Max

Guaranteed

−2 ±12

4 12

−2.8 +1

+4.7

0.9 2.7

±0.28

±0.6

±0.45

±0.9

1.0 1.25 1.5

1.4

4.3

780

1.4 1.44 1.5

−1.12

739

1.7 1.8 1.9

535 570

98 105

1.139

1.215

152

−95

−90

AD9639BCPZ-210

Min Typ Max

Guaranteed

−2 ±12

4 12

−2.8 +1

+4.7

0.9 2.7

±0.28

±0.6

±0.7 ±1.3

1.0 1.25 1.5

1.4

4.3

780

1.4 1.44 1.5

−1.12

737

1.7 1.8 1.9

610 650

111 120

1.298

1.386

173

−95

−90

Unit

Bits

% FS

LSB

V p-p

kΩ

MHz

mV/°C

µA

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.

2 AVDD/DRVDD, with link established.

3 Overrange condition is specified as 6 dB above the full-scale input range.

Rev. B | Page 3 of 36

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