AD7790 PDF даташит

Спецификация AD7790 изготовлена «Analog Devices» и имеет функцию, называемую «16-Bit Buffered Sigma-Delta ADC».

Детали детали

Номер произв	AD7790
Описание	16-Bit Buffered Sigma-Delta ADC
Производители	Analog Devices
логотип

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Data Sheet

FEATURES

Power

Supply: 2.5 V to 5.25 V operation

Normal: 75 μA maximum

Power-down: 1 μA maximum

RMS noise: 1.1 μV at 9.5 Hz update rate

16-bit p-p resolution

Integral nonlinearity: 3.5 ppm typical

Simultaneous 50 Hz and 60 Hz rejection

Internal clock oscillator

Programmable gain amplifier

Rail-to-rail input buffer

VDD monitor channel

Temperature range: –40°C to +105°C

10-lead MSOP

INTERFACE

3-wire serial

SPI®, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

APPLICATIONS

Smart transmitters

Battery applications

Portable instrumentation

Sensor measurement

Temperature measurement

Pressure measurement

Weigh scales

4 to 20 mA loops

Low Power, 16-Bit

Buffered Sigma-Delta ADC

AD7790

FUNCTIONAL BLOCK DIAGRAM

GND VDD

REFIN

VDD INTERNAL

CLOCK

AIN

BUF

16-BIT

ADC

DIGITAL

PGA

SERIAL

INTERFACE

AD7790

GND

Figure 1.

03538-0-001

GENERAL DESCRIPTION

The AD7790 is a low power, complete analog front end for

low frequency measurement applications. It contains a low

noise 16-bit ∑-Δ ADC with one differential input that can be

buffered or unbuffered along with a digital PGA, which allows

gains of 1, 2, 4, and 8.

The device operates from an internal clock. Therefore, the user

does not have to supply a clock source to the device. The output

data rate from the part is software programmable and can be

varied from 9.5 Hz to 120 Hz, with the rms noise equal to

1.1 μV at the lower update rate. The internal clock frequency

can be divided by a factor of 2, 4, or 8, which leads to a reduc-

tion in the current consumption. The update rate, cutoff

frequency, and settling time will scale with the clock frequency.

The part operates with a power supply from 2.5 V to 5.25 V.

When operating from a 3 V supply, the power dissipation for

the part is 225 μW maximum. It is housed in a 10-lead MSOP.

Rev. A

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-

sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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AD7790

TABLE OF CONTENTS

AD7790—Specifications.................................................................. 3

Timing Characteristics, ................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

On-Chip Registers .......................................................................... 10

Communications Register (RS1, RS0 = 0, 0) .......................... 10

Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x88) ... 11

Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02).... 11

Filter Register (RS1, RS0 = 1, 0; Power-on/Reset = 0x04)..... 12

Data Register (RS1, RS0 = 1, 1; Power-on/Reset = 0x0000) . 12

ADC Circuit Information.............................................................. 13

Overview...................................................................................... 13

Noise Performance ..................................................................... 13

REVISION HISTORY

3/13—Rev. 0 to Rev. A

Added ESD Caution Section ............................................................7

Changes to Figure 10.......................................................................15

Change to Reference Input Section...............................................17

Updated Outline Dimensions ........................................................19

Changes to Ordering Guide ...........................................................19

8/03—Revision 0: Initial Version

Data Sheet

Reduced Current Modes ........................................................... 13

Digital Interface.......................................................................... 14

Single Conversion Mode ....................................................... 15

Continuous Conversion Mode ............................................. 15

Continuous Read Mode ........................................................ 16

Circuit Description......................................................................... 17

Analog Input Channel ............................................................... 17

Programmable Gain Amplifier................................................. 17

Bipolar Configuration................................................................ 17

Data Output Coding .................................................................. 17

Reference Input........................................................................... 17

VDD Monitor ................................................................................ 18

Grounding and Layout .............................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. A | Page 2 of 20

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Data Sheet

AD7790—SPECIFICATIONS1

AD7790

Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = 0 V;

all specifications TMIN to TMAX, unless otherwise noted.)

Parameter

AD7790B

Unit

Test Conditions/Comments

ADC CHANNEL SPECIFICATION

Output Update Rate

9.5 Hz min nom

120 Hz max nom

ADC CHANNEL

No Missing Codes2

Bits min

±VREF Range, Update Rate ≤ 20 Hz

Resolution

Bits p-p

9.5 Hz Update Rate

Output Noise

1.1 µV rms typ

Integral Nonlinearity

±15 ppm of FSR max 3.5 ppm typ

Offset Error

±3 µV typ

Offset Error Drift vs. Temperature

±10

nV/°C typ

Full-Scale Error3

±10 µV typ

Gain Drift vs. Temperature

±0.5 ppm/°C typ

Power Supply Rejection

dB min

Input Range = ±REFIN, 100 dB typ

ANALOG INPUTS

Differential Input Voltage Ranges

±REFIN/GAIN V nom

REFIN = REFIN(+) – REFIN(–); GAIN = 1, 2, 4, or 8

Absolute AIN Voltage Limits2

GND + 100 mV V min

Buffered Mode of Operation

VDD – 100 mV

V max

Analog Input Current

Buffered Mode of Operation

Average Input Current2

±1 nA max

Average Input Current Drift

±5

pA/°C typ

Absolute AIN Voltage Limits2

GND – 30 mV V min

Unbuffered Mode of Operation

VDD + 30 mV

V max

Analog Input Current

Unbuffered Mode of Operation

Input current varies with input voltage.

Average Input Current

±400

nA/V typ

Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz

dB min

73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004

@ 50 Hz

dB min

90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014

@ 60 Hz

dB min

90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114

Common Mode Rejection

Input Range = ±REFIN, AIN = 1 V

@ DC

dB min

100 dB typ (FS[2:0] = 1004)

@ 50 Hz, 60 Hz2

100

dB min

50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114)

REFERENCE INPUT

REFIN = REFIN(+) – REFIN(–)

REFIN Voltage

2.5 V nom

Reference Voltage Range2

0.1 V min

V DD V max

Absolute REFIN Voltage Limits2

GND – 30 mV V min

VDD + 30 mV

V max

Average Reference Input Current

0.5

µA/V typ

Average Reference Input Current Drift

±0.03

nA/V/°C typ

1 Temperature Range –40°C to +105°C.

2 Specification is not production tested, but is supported by characterization data at initial product release.

3 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (VDD = 4 V).

4 FS[2:0] are the three bits used in the filter register to select the output word rate.

Rev. A | Page 3 of 20

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