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PDF 8S003F3 Data sheet ( Hoja de datos )
| Número de pieza | 8S003F3 | |
| Descripción | STM8S003F3 | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STM8S003F3 STM8S003K3
Value line, 16 MHz STM8S 8-bit MCU, 8 Kbyte Flash, 128 byte data
EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C
Datasheet - production data
Features
Core
• 16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
• Extended instruction set
Memories
• Program memory: 8 Kbyte Flash memory; data
retention 20 years at 55 °C after 100 cycles
• RAM: 1 Kbyte
• Data memory: 128 bytes true data EEPROM;
endurance up to 100 k write/erase cycles
Clock, reset and supply management
• 2.95 V to 5.5 V operating voltage
• Flexible clock control, 4 master clock sources
– Low-power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low-power 128 kHz RC
• Clock security system with clock monitor
• Power management
– Low-power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
– Permanently active, low-consumption
power-on and power-down reset
Interrupt management
• Nested interrupt controller with 32 interrupts
• Up to 27 external interrupts on 6 vectors
LQFP32
7x7 mm
TSSOP20
6.5x6.4 mm
UFQFPN20
3x3 mm
Timers
• Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
• 16-bit general purpose timers, with 3 CAPCOM
channels (IC, OC or PWM)
• 8-bit basic timer with 8-bit prescaler
• Auto wakeup timer
• Window and independent watchdog timers
Communications interfaces
• UART with clock output for synchronous
operation, SmartCard, IrDA, LIN master mode
• SPI interface up to 8 Mbit/s
• I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
• 10-bit ADC, ± 1 LSB ADC with up to 5
multiplexed channels, scan mode and analog
watchdog
I/Os
• Up to 28 I/Os on a 32-pin package including 21
high-sink outputs
• Highly robust I/O design, immune against
current injection
Development support
• Embedded single-wire interface module
(SWIM) for fast on-chip programming and non-
intrusive debugging
April 2016
This is information on a product in full production.
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www.st.com
1 page  
STM8S003F3 STM8S003K3
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
STM8S003F3/K3 value line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 15
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Legend/abbreviations for STM8S003F3/K3 pin description tables . . . . . . . . . . . . . . . . . . . 21
STM8S003K3 descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8S003F3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM8S003K3 alternate function remapping bits for 32-pin devices . . . . . . . . . . . . . . . . . . 44
STM8S003F3 alternate function remapping bits for 20-pin devices . . . . . . . . . . . . . . . . . . 45
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Total current consumption with code execution in run mode at VDD = 5 V . . . . . . . . . . . . 52
Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 53
Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 55
Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . 55
Total current consumption in halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 57
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy with RAIN < 10 kΩ , VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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STM8S003F3 STM8S003K3
3 Block diagram
Block diagram
Figure 1. STM8S003F3/K3 value line block diagram
Reset
Single wire
debug interface
400 Kbit/s
8 Mbit/s
LIN master
SPI emul.
up to 5
channels
1/2/4 kHz beep
Reset block
Reset
POR
BOR
Clock controller
Detector
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock to peripherals and core
STM8 core
Debug/SWIM
Window WDG
Independent WDG
8 Kbyte
program Flash
I2C
SPI
UART1
ADC1
Beeper
128 byte
data EEPROM
1 Kbyte RAM
16-bit advanced control
timer (TIM1)
16-bit general purpose
timer (TIM2)
Up to
4 CAPCOM
channels
+ 3 complementary
outputs
Up to
3 CAPCOM
channels
8-bit basic timer
(TIM4)
AWU timer
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8S003F3.PDF ] | |
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