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7851 PDF даташит

Спецификация 7851 изготовлена ​​​​«Analog Devices» и имеет функцию, называемую «AD7851».

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Номер произв 7851
Описание AD7851
Производители Analog Devices
логотип Analog Devices логотип 

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7851 Даташит, Описание, Даташиты
a
14-Bit 333 kSPS
Serial A/D Converter
AD7851
FEATURES
Single 5 V Supply
333 kSPS Throughput Rate/؎2 LSB DNL—A Grade
285 kSPS Throughput Rate/؎1 LSB DNL—K Grade
A & K Grades Guaranteed to 125؇C/238 kSPS
Throughput Rate
Pseudo-Differential Input with Two Input Ranges
System and Self-Calibration with Autocalibration on
Power-Up
Read/Write Capability of Calibration Data
Low Power: 60 mW typ
Power-Down Mode: 5 W typ Power Consumption
Flexible Serial Interface:
8051/SPI/QSPI/ P Compatible
24-Pin DIP, SOIC and SSOP Packages
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
Instrumentation and Control Systems
High Speed Modems
Automotive
AIN (+)
AIN (–)
REFIN/
REFOUT
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AGND
T/H
4.096 V
REFERENCE
BUF
AD7851
COMP
DVDD
DGND
AMODE
CREF1
CREF2
CAL
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY
AND CONTROLLER
SAR + ADC
CONTROL
CLKIN
CONVST
BUSY
SLEEP
SERIAL INTERFACE / CONTROL REGISTER
SM1 SM2 SYNC DIN DOUT SCLK POLARITY
http://www.DataSheet4U.net/
GENERAL DESCRIPTION
The AD7851 is a high speed, 14-bit ADC that operates from a
single 5 V power supply. The ADC powers-up with a set of
default conditions at which time it can be operated as a read-
only ADC. The ADC contains self-calibration and system-
calibration options to ensure accurate operation over time and
temperature and has a number of power-down options for low
power applications.
PRODUCT HIGHLIGHTS
1. Single 5 V supply.
2. Operates with reference voltages from 4 V to VDD.
3. Analog input ranges from 0 V to VDD.
4. System and self-calibration including power-down mode.
5. Versatile serial I/O port.
The AD7851 is capable of 333 kHz throughput rate. The input
track-and-hold acquires a signal in 0.33 µs and features a
pseudo-differential sampling scheme. The AD7851 has the
added advantage of two input voltage ranges (0 V to VREF, and
–VREF/2 to +VREF/2 centered about VREF/2). Input signal range
is to VDD and the part is capable of converting full-power signals
to 20 MHz.
CMOS construction ensures low power dissipation (60 mW typ)
with power-down mode (5 µW typ). The part is available in 24-
pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small
outline (SOIC) and 24-lead small shrink outline (SSOP) packages.
*Patent pending.
See Page 35 for data sheet index.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
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7851 Даташит, Описание, Даташиты
AD7851–SPECIFICATIONS1, 2 A Grade: fCLKIN = 7 MHz (–40؇C to +85؇C), fSAMPLE = 333 kHz; K Grade: fCLKIN = 6 MHz
(0؇C to +85؇C), fSAMPLE = 285 kHz; A and K Grade: fCLKIN = 5 MHz (to +125؇C), fSAMPLE =
238 kHz; (AVDD = DVDD = +5.0 V ؎ 5%, REFIN/REFOUT = 4.096 V External Reference; SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted)
Parameter
A1 K1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion Ratio3 (SNR) 77
Total Harmonic Distortion (THD)
–86
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Full Power Bandwidth
–87
–86
–86
20
78
–86
–87
–90
–90
20
dB min
dB max
dB max
dB typ
dB typ
MHz typ
Typically SNR is 79.5 dB
VIN = 10 kHz, Sine Wave, fSAMPLE = 333 kHz
VIN = 10 kHz, Sine Wave, fSAMPLE = 333 kHz,
Typically –96 dB
VIN = 10 kHz, fSAMPLE = 333 kHz
fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 333 kHz
fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 333 kHz
@ 3 dB
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Unipolar Offset Error
Positive Full-Scale Error
Negative Full-Scale Error
Bipolar Zero Error
14 14
±2 ±1
±2 ±1
± 10 ± 10
± 10 ± 10
± 10 ± 10
±1 ±1
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
LSB typ
Guaranteed No Missed Codes to 14 Bits
Review: “Adjusting the Offset Calibration
Register” in the “Calibration Registers” section
of the data sheet.
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
0 V to VREF 0 V to VREF
± VREF/2
± VREF/2
Volts
Volts
±1 ±1
20 20
µA max
pF typ
i.e., AIN(+) – AIN(–) = 0 V to VREF, AIN(–) can be
biased up but AIN(+) cannot go below AIN(–).
i.e., AIN(+) – AIN(–) = –VREF/2 to +VREF/2, AIN(–)
should be biased up and AIN(+) can go below
AIN(–) but cannot go below 0 V.
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range
Input Impedance
REFOUT Output Voltage
REFOUT Tempco
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
4/VDD
150
4/VDD
150
3.696/4.496 3.696/4.496
50 50
http://www.DataSheet4U.net/
V min/max
ktyp
V min/max
ppm/°C typ
Functional from 1.2 V
Resistor Connected to Internal Reference Node
VDD – 1.0
0.4
± 10
10
VDD – 1.0
0.4
± 10
10
V min
V max
µA max
pF max
VIN = 0 V or VDD
VDD – 0.4 VDD – 0.4
0.4 0.4
± 10 ± 10
10 10
Straight (Natural) Binary
2s Complement
V min
V max
µA max
pF max
ISOURCE = 200 µA
ISINK = 0.8 mA
Unipolar Input Range
Bipolar Input Range
CONVERSION RATE
Conversion Time
Conversion + T/H Acquisition Time
2.78
3.0
3.25
3.5
µs max
µs max
19.5 CLKIN Cycles
21 CLKIN Cycles Throughput Rate
–2–
REV. A
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7851 Даташит, Описание, Даташиты
AD7851
Parameter
A1
K1
Units
Test Conditions/Comments
POWER PERFORMANCE
AVDD, DVDD
IDD
Normal Mode5
Sleep Mode6
With External Clock On
With External Clock Off
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
+4.75/+5.25 +4.75/+5.25 V min/max
17 17 mA max AVDD = DVDD = 4.75 V to 5.25 V. Typically
12 mA.
20
600
10
300
89.25
105
52.5
20
600
10
300
89.25
105
52.5
µA typ
µA typ
µA max
µA typ
mW max
µW typ
µW max
Full Power-Down. Power management bits
in control register set as PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Typically 1 µA. Full Power-Down. Power
management bits in control register set as
PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
VDD = 5.25 V: Typically 63 mW; SLEEP = VDD.
VDD = 5.25 V; SLEEP = 0 V
VDD = 5.25 V; Typically 5.25 µW; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span7
Gain Calibration Span7
+0.05 × VREF/–0.05 × VREF V max/min Allowable Offset Voltage Span for Calibration
+1.025 × VREF/–0.975 × VREF V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES
1Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to +125°C.
2Specifications apply after calibration.
3SNR calculation includes distortion and noise components.
4Sample tested @ +25°C to ensure compliance.
5All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.
6CLKIN
@
DGND
when
external
clock
off.
All
digital
inputs
@
DGND
except
for
CONVST,
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SLEEP,
CAL,
and
SYNC
@
DVDD.
No
load
on
the
digital
outputs.
Analog inputs @ AGND.
7The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF, and the
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF). This is
explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. A
–3–
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