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PDF TFA9881 Data sheet ( Hoja de datos )
| Número de pieza | TFA9881 | |
| Descripción | 3.4 W PDM input class-D audio amplifier | |
| Fabricantes | NXP Semiconductors | |
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TFA9881
3.4 W PDM input class-D audio amplifier
Rev. 2 — 1 April 2011
Product data sheet
1. General description
The TFA9881 is a mono, filter-free class-D audio amplifier in a 9-bump WLCSP (Wafer
Level Chip-Size Package) with a 400 μm pitch.
The digital input interface is an over-sampled Pulse Density Modulated (PDM) bit stream.
The TFA9881 receives audio and control settings via this interface. Dedicated silence
patterns are used to configure the control settings of the device, such as mute, gain, Pulse
Width Modulated (PWM) output slope, clip control and bandwidth extension (this control
mechanism is not required if the default settings are used). The Power-down to Operating
mode transition is triggered when a clock signal is detected.
The device features low RF susceptibility because it has a digital input interface that is
insensitive to clock jitter. The second order closed loop architecture used in the TFA9881
provides excellent audio performance and high supply voltage ripple rejection.
2. Features and benefits
Small outline WLCSP9 package: 1.3 × 1.3 × 0.6 mm
Wide supply voltage range (fully operational from 2.5 V to 5.5 V)
High efficiency (90 %, 4 Ω/20 μH load) and low power dissipation
Quiescent power:
www.DataSheet.net/
6.5 mW (VDDD = 1.8 V, VDDP = 3.6 V, 4 Ω/20 μH load, fclk = 2.048 MHz)
7.8 mW (VDDD = 1.8 V, VDDP = 3.6 V, 4 Ω/20 μH load, fclk = 6.144 MHz)
Output power:
1.4 W into 4 Ω at 3.6 V supply (THD = 1 %)
2.7 W into 4 Ω at 5.0 V supply (THD = 1 %)
3.4 W into 4 Ω at 5.0 V supply (THD = 10 %)
Output noise voltage: 24 μV (A-weighted)
Signal-to-noise ratio: 103 dB (VDDP = 5 V, A-weighted)
Fully short-circuit proof across load and to supply lines
Current limiting to avoid audio holes
Thermally protected
Undervoltage and overvoltage protection
High-pass filter for DC blocking
Invalid data protection
Simple two-wire interface for audio and control settings
Left/right selection
Three gain settings: −3 dB, 0 dB and +3 dB
PWM output slope setting for EMI reduction
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
NXP Semiconductors
TFA9881
3.4 W PDM input class-D audio amplifier
8. Functional description
The TFA9881 is a high-efficiency mono Bridge Tied Load (BTL) class-D audio amplifier
with a digital stereo PDM input interface. A High-Pass (HP) filter removes the DC
components from the incoming PDM stream. This stream is subsequently converted into
two PWM signals. A 3-level PWM scheme supports filterless speaker drive.
8.1 Mode selection and interfacing
The TFA9881 supports four operating modes:
• Power-down mode, with low supply current
• Mute mode, in which the output stages are floating so that the audio input signal is
suppressed
• Operating mode, in which the amplifier is fully operational, delivering an output signal
• Fault mode
The TFA9881 switches to Fault mode automatically when a protection mechanism is
activated (see Section 8.6). The defined patterns required on the CLK and DATA inputs to
select the other three modes are given in Table 4.
Power-down mode is selected when there is no clock signal on the CLK input. Applying
the clock signal will cause the TFA9881 to switch from Power-down mode to Operating
mode. Power-down mode is also activated when the power-down silence pattern (at least
128 consecutive 0xAC bytes) is detected on the DATA input (see Section 8.4.1). The
TFA9881 will switch to Power-down modewww.DataSheet.net/ after byte 128 and will remain in Power-down
mode as long as a continuous stream of consecutive 0xAC bytes is being received. It will
switch to Operating mode if a byte other than 0xAC is received.
Mute mode is activated when the mute silence pattern (at least 32 consecutive 0x66
bytes) is detected on the DATA input. The TFA9881 will switch to Mute mode after byte 32
and will remain in Mute mode until a byte other than 0x66 is received.
Table 4. Mode selection
Mode
Pins
CLK frequency
Power-down 0 Hz
2 MHz to 8 MHz
Mute
2 MHz to 8 MHz
Operating 2 MHz to 8 MHz
Data pattern
don’t care
activated after 128 consecutive 0xAC bytes
activated after 32 consecutive 0x66 bytes
PDM bit stream
OUTA, OUTB
floating
floating
floating
switching
8.2 Digital stereo PDM audio input
The TFA9881 supports the digital stereo PDM stream illustrated in Figure 5. Table 5
shows the pin control configuration for left and right selection.
TFA9881
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 April 2011
© NXP B.V. 2011. All rights reserved.
5 of 32
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
NXP Semiconductors
TFA9881
3.4 W PDM input class-D audio amplifier
8.5 High-pass filter
The high-pass filter will block the DC components in the incoming audio stream. The
cut-off frequency, fhigh(−3dB), is determined by the clock frequency, and is defined in
Equation 1:
fhigh(–3dB) = –----f--c--l--k---⋅---l-1-n--6--(--8-⋅--1-k--9--⋅-1--π---⁄--8---1---9---2----)
(1)
where k depends on the bandwidth extension setting (see Section 8.4.6):
• k = 2 if bandwidth extension is off
• k = 1 if bandwidth extension is on
fhigh(−3dB) is about 7.5 Hz at a clock frequency of 6.144 MHz when bandwidth extension is
off. The high-pass filter is always enabled.
Remark: Care should be taken when DC dither is applied to the PDM audio input stream.
The PDM source should slowly increase this DC-dither to avoid pop noise.
8.6 Protection mechanisms
The following protection circuits are included in the TFA9881:
• Invalid Data Protection (IDP)
• OverTemperature Protection (OTP)
• OverVoltage Protection (OVP) www.DataSheet.net/
• UnderVoltage Protection (UVP)
• OverCurrent Protection (OCP)
The reaction of the device to fault conditions differs depending on the protection circuit
involved.
8.6.1 Invalid Data Protection (IDP)
IDP is designed to detect the absence of a data input signal. IDP is activated when 128
consecutive 0s or 1s are received on the DATA input.
IDP is disabled when a PDM stream that does not contain 128 consecutive 0s or 1s is
received. The output stages are set floating when IDP is active.
Remark: The maximum PDM input modulation depth should be limited to avoid false IDP
triggering.
8.6.2 OverTemperature Protection (OTP)
OTP prevents heat damage to the TFA9881. It is triggered when the junction temperature
exceeds 130 °C. When this happens, the output stages are set floating. OTP is cleared
automatically via an internal timer (100 ms with fclk = 6.144 MHz), after which the output
stages will start to operate normally again.
TFA9881
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 April 2011
© NXP B.V. 2011. All rights reserved.
11 of 32
Datasheet pdf - http://www.DataSheet4U.co.kr/
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