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PDF RTL8201L Data sheet ( Hoja de datos )
| Número de pieza | RTL8201L | |
| Descripción | SINGLE CHIP SINGLE PORT 10/100MBPS FAST ETHERNET PHYCEIVER | |
| Fabricantes | REALTEK | |
| Logotipo |  |
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1. RTL8201L  Hay una vista previa y un enlace de descarga de RTL8201L (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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RTL8201(L)
REALTEK SINGLE CHIP
SINGLE PORT 10/100MBPS
FAST ETHERNET PHYCEIVER
RTL8201(L)
1. Features........................................................................ 2
2. General Description .................................................... 2
3. Block Diagram............................................................. 3
4. Pin Assignments .......................................................... 4
5. Pin Description ............................................................ 5
5.1 100 Mbps MII & PCS Interface ............................. 5
5.2 Serial Network Interface (SNI) .............................. 5
5.3 Clock Interface ....................................................... 5
5.4 100Mbps Network Interface................................... 6
5.5 Device Configuration Interface .............................. 6
5.6 LED Interface/PHY Address Config...................... 6
5.7 Reset and Test pins................................................. 6
5.8 Power and Ground pins .......................................... 6
6. Register Descriptions .................................................. 7
6.1 Register 0 Basic Mode Control .............................. 7
6.2 Register 1 Basic Mode Status................................. 9
6.3. Register 2 PHY Identifier 1................................. 10
6.4. Register 3 PHY Identifier 2................................. 10
6.5. Register 4 Auto-negotiation Advertisement................ 11
6.6 Register5Auto-NegotiationLinkPartnerAbility.................. 12
6.7 Register 6 Auto-negotiation Expansion (ANER) . 14
6.8 Register16NwaySetup(NSR)....................................... 14
6.9 Register17Loopback,Bypass,ReceiverErrorMask(LBREMR).... 15
6.10 Register 18 RX_ER Counter (REC)................... 15
6.11 Register1910MbpsNetworkInterfaceConfiguration.......... 15
6.12 Register 20 PHY 1_1.......................................... 15
6.13 Register 21 PHY 1_2.......................................... 16
6.13 Register 22 PHY 2 ............................................. 16
6.14 Register 23 Twister_1 ........................................ 16
6.15 Register 24 Twister_2 ........................................ 16
7. Functional Description ............................................. 17
7.1 MII and Management Interface............................ 17
7.2 Auto-negotiation and Parallel Detection .............. 18
7.3 Flow control support ............................................ 18
7.4 Hardware Configuration and Auto-negotiation.............. 19
7.5 LED and PHY Address Configuration................. 20
7.6 Serial Network Interface ...................................... 20
7.7 PowerDown,LinkDown,PowerSaving,andIsolationModes 21
7.8 Media Interface .................................................... 21
7.8.1 100Base Tx/Rx ............................................. 21
7.8.2 10Base Tx/Rx ............................................... 22
7.9 Repeater Mode Operation .................................... 22
7.10 Reset, Power, and Transmit Bias........................ 22
8. Electrical Characteristics ......................................... 23
8.1 D.C. Characteristics ............................................. 23
8.1.1. Absolute Maximum Ratings ........................ 23
8.1.2. Operating Conditions................................... 23
8.1.3. Power Dissipation........................................ 23
8.1.4 Supply Voltage: Vcc ..................................... 23
8.2 A.C. Characteristics ............................................. 24
8.2.1 Transmission Without Collision ................... 24
8.2.2 Reception Without Error............................... 24
9. Mechanical Dimensions ............................................ 25
2002-01-18
1
Rev.1.04
http://www.cornelius-consult.de
1 page  
www.DataSheet4U.net
RTL8201(L)
5. Pin Description
5.1 100 Mbps MII & PCS Interface
Symbol
TXC
TXEN
TXD[3:0]
RXC
COL
CRS
RXDV
RXD[3:0]
RXER
MDC
MDIO
Type
O
I
I
O
O
I/O
O
O
O
I
I/O
Pin(s) No.
7
2
3, 4, 5, 6
16
1
23
22
18, 19, 20, 21
24
25
26
Description
Transmit Clock: This pin provides a continuous clock as a timing reference
for TXD[3:0] and TXEN.
Transmit Enable: The input signal indicates the presence of a valid nibble
data on TXD[3:0].
Transmit Data: MAC will source TXD[0..3] synchronous with TXC when
TXEN is asserted.
Receive Clock: This pin provides a continuous clock reference for RXDV
and RXD[0..3] signals. RXC is 25MHz in the 100Mbps mode and 2.5Mhz in
the 10Mbps mode.
Collision Detected: COL is asserted high when a collision is detected on the media.
Carrier Sense: This pin’s signal is asserted high if the media is not in IDEL state.
Receive Data Valid: This pin’s signal is asserted high when received data is
present on the RXD[3:0] lines; the signal is deasserted at the end of the
packet. The signal is valid on the rising of the RXC.
Receive Data: These are the four parallel receive data lines aligned on the
nibble boundaries driven synchronously to the RXC for reception by the
external physical unit (PHY).
Receive error: if any 5B decode error occurred such as invalid J/K, T/R,
invalid symbol, this pin will go high
Management Data Clock: This pin provides a clock synchronous to MDIO,
which may be asynchronous to the transmit TXC and receive RXC clocks.
Management Data Input/Output: This pin provides the bi-directional
signal used to transfer management information.
5.2 Serial Network Interface (SNI)
10Mbps only
Symbol
COL
RXD0
CRS
RXC
TXD0
TXC
TXEN
Type
O
O
O
O
I
O
I
Pin(s) No.
1
21
23
16
6
7
2
Description
Collision Detect
Received Serial Data
Carrier Sense
Receive Clock: Resolved from received data
Transmit Serial Data
Transmit Clock: Generate by PHY
Transmit Enable: For MAC to indicate transmit operation
5.3 Clock Interface
Symbol
X2
X1
Type
O
I
Pin(s) No.
47
46
Description
25Mhz Crystal Output: This pin provides the 25MHz crystal output.
25Mhz Crystal Input: This pin provides the 25MHz crystal input.
2002-01-18
5
Rev.1.04
http://www.cornelius-consult.de
5 Page 
www.DataSheet4U.net
RTL8201(L)
6.5. Register 4 Auto-negotiation Advertisement
(ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner during
Auto-negotiation.
Address
Name
Description/Usage
Default/Attribute
4:<15>
NP
Next Page: The RTL8201L does not implement the Next Page function,
0, RO
so bit 15 will always return a ‘0’ when read.
4:<14>
ACK
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
Acknowledge: Because the Next Page function is not implemented, bit
14 will always return a ‘0’ when read.
0, RO
4:<13>
1: Acknowledge reception of link partner capability data word
0: Do not acknowledge reception
RF
Remote Fault: Bit 13 returns a value of ‘1’ when the RTL8201L has
0, RW
detected a remote fault. The RTL8201L advertises this information, but
does not act upon it.
4:<12:11>
4:<10>
Reserved
Pause
1: Advertise remote fault detection capability
0: Do not advertise remote fault detection capability
Reserved: Ignore the output of the RTL8201L when these bits are
read.
Pause: The use of this bit is independent of the negotiated data rate,
medium, or link technology. Setting this bit indicates the availability of
additional DTE capabilities when full duplex operation is in use. This
bit is used by one MAC to communicate Pause Capability to its Link
Partner and has no effect on PHY operation.
0, RW
4:<9>
1: Flow control is supported by local node
0: Flow control is NOT supported by local node
T4
100Base-T4: This bit advertises the ability to the Link Partner that the
0, RO
RTL8201L can operate in 100Base-T4 mode. Writing a ‘0’ to this bit
will suppress the transmission of this ability to the Link Partner.
Resetting the chip will restore the default value. The default value is ‘1’
and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return the
last written value or the default value if no write has been completed
since the last reset.
4:<8>
TXFD
1: 100Base-T4 is supported by local node
0: 100Base-T4 not supported by local node
100Base-TX-FD: This bit advertises the ability to the Link Partner that
the RTL8201L can operate in 100Base-TX full duplex mode. Writing a
‘0’ to this bit will suppress the transmission of this ability to the Link
Partner. Resetting the chip will restore the default value. The default
value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will
return the last written value or the default value if no write has been
completed since the last reset.
1, RW
4:<7>
1: 100Base-TX full duplex is supported by local node
0: 100Base-TX full duplex not supported by local node
TX
100Base-TX: This bit advertises the ability to the Link Partner that the
1, RW
RTL8201L can operate in 100Base-TX half duplex mode. Writing a ‘0’
to this bit will suppress the transmission of this ability to the Link
Partner. Resetting the chip will restore the default value. The default
value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will
return the last written value or the default value if no write has been
completed since the last reset.
1: 100Base-TX is supported by local node
0: 100Base-TX not supported by local node
2002-01-18
11
Rev.1.04
http://www.cornelius-consult.de
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet RTL8201L.PDF ] | |
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