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PDF TLE8263-2E Data sheet ( Hoja de datos )
| Número de pieza | TLE8263-2E | |
| Descripción | Universal System Basis Chip | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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Data Sheet, Rev. 1.0, March 2009
TLE8263-2E
Universal System Basis Chip
HERMES
Rev. 1.0
Automotive Power
1 page  
TLE8263-2E
Confidential
HERMES Overview
HS CAN Transceiver
• Compliant to ISO 11898-2 and 11898-5 as well as SAE J2284
• CAN data transmission rate up to 1 MBaud
• Supplied by dedicated input VccHSCAN
• Low power mode management
• Bus wake-up capability via CAN message
• Excellent EMC performance (very high immunity and very low emission)
• Bus pins are short circuit proof to ground and battery voltage
• 8 kV ESD gun test on CANH / CANL / SPLIT
• Bus failure detection
LIN Transceiver
• LIN2.1 conformance, LIN2.1 is back compatible to LIN1.3 and LIN2.0
• SAE J2602-2 conformance
• Compatible to ISO 9141 (K-L-Line)
• Transmission rate up to 20 kBaud, LIN Flash Mode 115kBaud
• 8 kV ESD gun test on Bus pins
Voltage Regulators
• Low-dropout voltage regulator
• Vcc1µC, 200 mA, 5 V ±2% for external devices, such as microcontroller and RF receiver
• Vcc2, 200 mA, 5 V ±2% for external devices or the internal HS CAN cell
• Vcc3, current limitation by shunt resistor (up to 400 mA with 220 mΩ shunt resistor), 5 V ±4% with external PNP
transistor; for example: to supply additional external CAN transceivers
• Vcc1µC, undervoltage Time-out
Supervision
• Reset output with integrated pull-up resistor
• Time-out or Window Watchdog, SPI configured
• Watchdog Timer from 16 ms to 1024 ms
• Check sum bit for Watchdog configuration
• Reset due to Watchdog failure can be inhibited with Test pin (SBC SW Development Mode)
Interrupt Management
• Complete enabling / disabling of interrupt sources
• Timing filter mechanism to avoid multiple / infinite Interrupt signals
Limp Home
• Open drain Limp Home outputs
• Dedicated internal logic supply
• Maximum safety architecture for Safety Operation Mode
• Configurable Fail-Safe behavior
• Dedicated side indicators signal 1.25Hz 50% duty cycle
• Dedicated PWM signal 100Hz 20% duty cycle
Data Sheet
5 Rev. 1.0, 2009-03-31
5 Page 
TLE8263-2E
Confidential
State Machine
4.2 State Machine Description
The System Basis Chip (SBC) offers ten operating modes: Power On Reset, Init, Normal, Restart, Software Flash,
Sleep, Stop, Fail-Safe, Software Development, and Factory Flash Mode. The modes are controlled with one test
pin and via three mode select bits MS2..0, within the SPI. Additionally, the SBC allows five configurations,
accessed via two external pins and one SPI bit.
4.2.1
Configuration Description
Table 1 provides descriptions and conditions for entry to the different configurations of the SBC.
Table 1 SBC Configuration
Configuration Description
Test pin INT Pin WD to
LH bit
config 0
config 1
Software Development Mode
After missing the WD trigger for the first time, the state of Vcc1µC
remain unchanged, LH pin is active, SBC in Restart Mode
0V n.a
Open / VS External
pull-up
n.a
0
config 2
After missing the WD trigger for the first time, Vcc1µC turns OFF,
LH pin is active, SBC in Fail-Safe Mode
No ext. 0
pull-up
config 3
config 4
After missing the WD trigger for the second time, the state of
Vcc1µC remain unchanged, LH pin is active, SBC in Restart
Mode
After missing the WD trigger for the second time, Vcc1µC turns
OFF, LH pin is active, SBC in Fail-Safe Mode
External 1
pull-up
No ext. 1
pull-up
In SBC SW Development Mode, Config 1 to 4 are accessible.
4.2.2
SBC Power ON Reset (POR)
At VS > VUVON, the SBC starts to operate, by reading the test pin and then by turning ON Vcc1µC. When Vcc1µC
reaches the reset threshold VRT1, the reset output remains activated for tRD1 and the SBC enters then the Init Mode.
In the event that Vs decreases below VUVOFF, the device is completely disabled. For more details on the disable
behavior of the SBC blocks, please refer to the chapter specific to each block.
4.2.3
SBC Init Mode
At entering the SBC Init Mode, the SBC starts to read the Test pin. The SBC starts-up in SBC Init Mode, and, after
powering-up, waits for the microcontroller to finish its startup and initialization sequences. Vcc2/3 are OFF and the
Watchdog is configurable but not active. CAN and LIN modules are inactive and Limp Home output is inactive.
From this transition mode, the SBC can be switched via SPI command to the desired operating mode, SBC Normal
or Software Flash Mode. If the SBC does not receive any SPI command, or receive wrong SPI command (i.e. not
send the device to SBC Normal or SBC SW Flash Mode) within a 256 ms time frame after the reset relaxation, it
will enter into SBC Restart Mode and activate the Limp Home output.
Note: In Init Mode it is recommended to send one SPI command that sets the device to Normal Mode, triggers the
watchdog the first time and sets the required watchdog settings.
Data Sheet
11 Rev. 1.0, 2009-03-31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TLE8263-2E.PDF ] | |
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