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PDF 82580 Data sheet ( Hoja de datos )
| Número de pieza | 82580 | |
| Descripción | Quad/Dual GbE LAN Controller | |
| Fabricantes | Intel | |
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Intel® 82580 Quad/Dual GbE LAN
Controller Specification Update
LAN Access Division (LAD)
322444-007EN
Revision 2.34
October 2010
1 page  
Intel® 82580 Quad/Dual GbE LAN Controller
1.1 Introduction and Scope
This document is an update to the Intel® 82580 Quad/Dual Port GbE LAN Controller Datasheet. It is
intended for use by system manufacturers and software developers. All product documents are subject
to frequent revision. Be sure you have the latest information before finalizing your design.
References to PCIe* in this document refer to PCIe v2.0 (5Gbps).
1.2 Product and Device Identification
Table 1. 82580 Product and Device Indentification
MM#
905781
Stepping
A1
Top Marking
NH82580EB
Specification #
S LH5P
Status & Media
Production, T&R
905782
A1
NH82580EB
S LH5Q
Production, Tray
905783
A1
NH82580EK
S LH5R
Production, T&R
905784
A1
NH82580EK
S LH5S
Production, Tray
905785
A1
NH82580DB
S LH5T
Production, T&R
905786
A1
NH82580DB
S LH5U
Production, Tray
904983
A1
NH82580EB
Q MQR
Engineering, Tray
904984
A1
NH82580EK
Q MQS
Engineering, Tray
904985
A1
NH82580DB
Q MQT
Engineering, Tray
903315
A0
NH82580EB
Q LSY
Engineering, Tray
Description
1 Gbs, 4-port
1 Gbs 4-port SERDES
1 Gbs, 2-port
1 Gbs, 4 port
1 Gbs, 4-port SERDES
1 Gbs, 2-port
1 Gbs, 4-port
322444-007EN
Revision 2.34
October 2010
Intel® 82580 Quad/Dual GbE LAN Controller
Specification Update
5
5 Page 
Intel® 82580 Quad/Dual GbE LAN Controller
Workaround:
1. SW should not execute bit bang sequences longer than one word at a time.
2. When SW reads the EEC/FLA, it should make sure that it still has the request and
grant; if not it should renew it and re-start the transaction (this does not cover all cases
but reduces the possibility of a problem).
Status:
A1 NoFix
3. Possible System Hang During Enable/Disable When Connecting through nVIdia* IO55 Slot
Problem:
Once the link is up, when the 82580 tries to connect with the nVidia IO55 chipset, the
following may occur:
• The Link layer tries to train but not all lanes work.
• The 82580 tries retraining with fewer lanes; but during retraining may loop.
• The system hangs.
Implication: The 82580 cannot reliably connect using this configuration.
Workaround: Connecting to a different port on the system.
Status:
A1 NoFix
4. SMBus: EEPROM Not Written On ARP If the EEPROM Semaphore Is Taken by SW
Problem:
If an SMBus ARP address is stored at the same time the EEPROM is locked by SW, the
address is not be saved.
Implication : Wrong SMBus address after FW reset.
Workaround: Set the SMBus address in the EEPROM (not through ARP).
Status:
A1 NoFix
5. PCIe Links at x1 Instead of x4 When Attached to Certain Chipset Ports
Problem:
When the device is connected to certain PCIe x4 ports, the PCIe link is x1 instead of x4.
The affected ports on Intel devices have a Device ID of 0x2690. These ports can be found
on:
• 631xESB/632xESB - I/O Controller Hub
• INTEL 3100 SCH Port B
Implications: If the PCIe link is x1, the bandwidth is limited and might not be sufficient for all device
ports, resulting in a performance bottleneck.
Workaround: Do not attach the device to this chipset port. If such a connection cannot be avoided,
please contact your Intel representative for assistance.
322444-007EN
Revision 2.34
October 2010
Intel® 82580 Quad/Dual GbE LAN Controller
Specification Update
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet 82580.PDF ] | |
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