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73M1903C PDF даташит

Спецификация 73M1903C изготовлена ​​​​«Teridian Semiconductor» и имеет функцию, называемую «Modem Analog Front End».

Детали детали

Номер произв 73M1903C
Описание Modem Analog Front End
Производители Teridian Semiconductor
логотип Teridian Semiconductor логотип 

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73M1903C Даташит, Описание, Даташиты
Simplifying System IntegrationTM
DS_1903C_033
DESCRIPTION
The 73M1903C Analog Front End (AFE) IC includes
fully differential hybrid driver outputs, which connect to
the telephone line interface through a transformer-
based DAA. The receive pins are also fully differential
for maximum flexibility and performance. This
arrangement allows for the design of a high
performance hybrid circuit to improve signal to noise
performance under low receive level conditions, and
compatibility with any standard transformer intended
for PSTN communications applications.
The device incorporates a programmable sample rate
circuit to support soft modem and DSP based
implementations of all speeds up to V.92 (56 kbps).
The sampling rates supported are from 7.2 kHz to
16.0 kHz by programming the pre-scaler NCO and the
PLL NCO.
The 73M1903C device incorporates a digital host
interface that is compatible with the serial ports found
on most commercially available DSPs and processors
and exchanges both payload and control information
with the host. This interface can be configured as a
single master/slave mode or as a daisy chain mode
that allows the user to connect up to eight 73M1903C
devices to a single host for multi Analog Front End
applications, such as, central server modems.
Costs saving features of the device include an input
reference frequency circuit, which accepts a range of
crystals from 4.9-27 MHz. It also accepts external
reference clock values between 1 MHz and 40 MHz
generated by the host processor. In most
applications, this eliminates the need for a dedicated
crystal oscillator and reduces the bill of materials
(BOM).
The 73M1903C also supports two analog loop back
and one digital loop back test modes.
73M1903Cwww.DataSheet4U.com
Modem Analog Front End
DATA SHEET
March 2010
FEATURES
Two pairs of software selectable transmit
differential outputs for worldwide impedance
driver implementations.
Up to 56 kbps (V.92) performance
Programmable sample rates (7.2-16.0 kHz)
Reference clock range of 1-40 MHz
Crystal frequency range of 4.9-27 MHz
Master or slave mode operation
Daisy chain configurable synchronous serial
Host interface
Low power modes
Fully differential receiver and transmitter
Drivers for transformer interface
3.0 V – 3.6 V operation
5 V tolerant I/O
Industrial temperature range (-40 to +85 °C)
JATE compliant transmit spectrum
Package option: 32-pin QFN
APPLICATIONS
Central site server modems
Set Top Boxes
Personal Video Recorders (PVR)
Multifunction Peripherals (MFP)
Fax Machines
Internet Appliances
Game Consoles
Point of Sale Terminals
Automatic Teller Machines
Speaker Phones
Digital Answering Machines
RF Modems
TXAP1
TXAN1
TXAP2
TXAN2
RXAP
RXAN
(HYBRID)
Transmit
Drivers/
Filters
Analog
Sigma
Delta
VBG
Ref.
Receiver
MUX/
Filters
DAC
Control
Registers
Serial
Port
GPIO
HOOK
DAA
controls
Clock
Control
Logic
SCLK
SDIN
SDOUT
FS
FSD
Crystal
Rev. 5.0
1









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73M1903C Даташит, Описание, Даташиты
73M1903C Data Sheet
DSw_w1w9.0D3atCaS_he0e3t43U.com
Table of Contents
1 Pin Description................................................................................................................................ 4
2 Modem Analog Front End (MAFE) Serial Interface ........................................................................ 6
2.1 Serial Data and Control.............................................................................................................. 7
2.2 Slave Mode and DAISY CHAIN ............................................................................................... 10
2.3 Control Register Map ............................................................................................................... 12
3 System Control Registers............................................................................................................. 13
4 GPIO Registers.............................................................................................................................. 15
5 PLL Configuration Registers ........................................................................................................ 16
6 Clock Generation........................................................................................................................... 19
6.1 Crystal Oscillator and Prescaler NCO ...................................................................................... 19
6.2 Analog I/O ............................................................................................................................... 22
6.3 Modem Transmitter.................................................................................................................. 23
6.4 Transmit Levels ....................................................................................................................... 24
6.5 Transmit Power – dBm ............................................................................................................ 25
6.6 Modem Receiver ..................................................................................................................... 26
7 Test Modes .................................................................................................................................... 29
7.1 Power Saving Modes ............................................................................................................... 29
8 Electrical Specifications ............................................................................................................... 30
8.1 Absolute Maximum Ratings ..................................................................................................... 30
8.2 Recommended Operating Conditions....................................................................................... 30
8.3 Digital Specifications................................................................................................................ 31
8.3.1 DC Characteristics........................................................................................................ 31
8.4 AC Timing ............................................................................................................................... 32
9 Analog Specifications................................................................................................................... 33
9.1 DC Specifications .................................................................................................................... 33
9.2 AC Specifications .................................................................................................................... 33
9.3 Performance............................................................................................................................ 34
9.3.1 Receiver....................................................................................................................... 34
9.3.2 Transmitter................................................................................................................... 35
10 Mechanical Drawings.................................................................................................................... 37
11 Ordering Information..................................................................................................................... 38
Appendix A .......................................................................................................................................... 39
73M1903C DAA Resistor Calculation Guide .................................................................................... 39
Trans-Hybrid Loss (THL) ................................................................................................................. 41
Appendix B .......................................................................................................................................... 42
Crystal Oscillator ............................................................................................................................. 42
PLL 43
Examples of NCO Settings .............................................................................................................. 44
Example 1 ............................................................................................................................... 44
Example 2 ............................................................................................................................... 45
Example 3 ............................................................................................................................... 46
Example 4 ............................................................................................................................... 47
Revision History .................................................................................................................................. 48
2 Rev. 5.0









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73M1903C Даташит, Описание, Даташиты
DS_1903C_033
73M1903CwwDwa.DtaataSShheeete4Ut .com
Figures
Figure 1: SCLK and FS with SckMode=0 ................................................................................................. 8
Figure 2: Control Frame Position versus SPOS........................................................................................ 8
Figure 3: Serial Port Timing Diagrams ..................................................................................................... 9
Figure 4: 73M1903C Host Connection in Master and Slave Modes ........................................................ 10
Figure 5: 73M1903C Daisy Chaining for Master/Slave Mode and Slave Modes ...................................... 10
Figure 6: Clock Generation .................................................................................................................... 19
Figure 7: Analog Block Diagram............................................................................................................. 22
Figure 8: Overall TX Path Frequency Response at 8 kHz Sample Rate.................................................. 23
Figure 9: Frequency Response of TX Path for DC to 4 kHz in Band Signal at 8 kHz Sample Rate.......... 24
Figure 10: Overall Receiver Frequency Response at 8 kHz Sample Rate............................................... 26
Figure 11: Rx Passband Response at 8 kHz Sample Rate..................................................................... 27
Figure 12: RXD Spectrum of 1 kHz Tone ............................................................................................... 28
Figure 13: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes....... 28
Figure 14: Serial Port Data Timing ......................................................................................................... 32
Figure 15: Typical DAA Block Diagram .................................................................................................. 39
Figure 16: Single Transmitter Arrangement............................................................................................ 40
Figure 17: Dual transmitter arrangement................................................................................................ 41
Figure 18: NCO Block Diagram.............................................................................................................. 42
Figure 19: PLL Block Diagram ............................................................................................................... 43
Tables
Table 1: 32 QFN Pin Description.............................................................................................................. 4
Table 2: Register Map ........................................................................................................................... 12
Table 3: Fvco and Kvco Settings at 25°C ............................................................................................... 16
Table 4: PLL Power Down ..................................................................................................................... 18
Table 5: Clock Generation Register Settings for Fxtal = 27 MHz ............................................................ 19
Table 6: Clock Generation Register Settings for Fxtal = 24.576 MHz...................................................... 20
Table 7: Clock Generation Register Settings for Fxtal = 9.216 MHz........................................................ 20
Table 8: Clock Generation Register Settings for Fxtal = 24.000 MHz...................................................... 21
Table 9: Clock Generation Register Settings for Fxtal = 25.35 MHz........................................................ 21
Table 10: Peak to RMS Ratios and Maximum Transmit.......................................................................... 25
Table 11: Receive Gain ......................................................................................................................... 26
Table 12: Absolute Maximum Ratings.................................................................................................... 30
Table 13: Recommended Operation Conditions ..................................................................................... 30
Table 14: DC Characteristics ................................................................................................................. 31
Table 15: Serial Interface Timing ........................................................................................................... 32
Table 16: Reference Voltage Specifications ........................................................................................... 33
Table 17: Maximum Transmit Levels...................................................................................................... 33
Table 18: Receiver Performance Specifications ..................................................................................... 34
Table 19: Transmitter Performance Specifications ................................................................................. 35
Rev. 5.0
3










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