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Número de pieza | 68HC05C5 | |
Descripción | SPECIFICATION (General Release) | |
Fabricantes | Freescale Semiconductor | |
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HC0w5wCw5.DGataRShSeet/4DU.com
REV 1.2
68HC05C5
SPECIFICATION
(General Release)
©August 29, 1994
CSIC System Design Group
Austin, Texas
For More Information On This Product,
Go to: www.freescale.com
1 page Freescale SemiconducMtCo6r8,HICn0c5.C5 Specification Rev. 1.2
LIST OF FIGURES
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Figure 1-1:
Figure 2-1:
Figure 2-2:
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 4-1:
Figure 4-2:
Figure 4-3:
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Figure 4-5:
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Figure 5-1:
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Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 9-1:
Figure 9-2:
Figure 9-3:
Self-Check Mode Schematic for the MC68HC05C5 .................................2
Single-Chip Mode Pinout of the MC68HC05C5........................................6
Self-Check Mode Schematic for the MC68HC05C5 .................................7
The 8K Memory Map of the MC68HC05C5 ..............................................9
I/O Registers for the MC68HC05C5 .......................................................10
Programming Register ............................................................................11
Programming Model ...............................................................................15
Stacking Order ........................................................................................15
Power-On Reset and RESET .................................................................23
Interrupt Flowchart ..................................................................................27
Stop Recovery Timing Diagram ..............................................................28
STOP/WAIT Flowcharts..........................................................................29
Port I/O Circuitry .....................................................................................32
Timer Block Diagram ..............................................................................33
Timer Control Register............................................................................35
Timer Status Register .............................................................................37
SIOP Block Diagram ...............................................................................39
Serial I/O Port Timing (CPOL=1) ............................................................40
Serial I/O Port Timing (CPOL=0) ............................................................40
SIOP Control Register ............................................................................40
SIOP Status Register..............................................................................42
SIOP Data Register ................................................................................42
Stop Recovery Timing Diagram ..............................................................48
LVPI Timing Diagram..............................................................................48
SIOP Timing Diagram .............................................................................49
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Go to: www.freescale.com
Page vii
5 Page Freescale SemicondMuCc6t8oHrC,0I5nCc5.Specification Rev. 1.2
www.DataSheet4U.com
SECTION 2
OPERATING MODES
The MCU has two modes of operation: Single-Chip Mode and Self-Check Mode. Table
2-1 shows the conditions required to go into each mode, where VTST = 2 x VDD.
Table 2-1: Operating Mode Conditions
RESET
IRQ
VSS to VDD
VTST
TCAP
VSS to VDD
VDD
MODE
Single-chip
Self-Check
2.1 SINGLE-CHIP MODE
In Single-Chip Mode, the address and data buses are not available externally, but there
are four 8-bit I/O ports. This mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral functions. All
address and data activity occurs within the MCU. Single-Chip Mode is entered on the
rising edge of RESET if the IRQ pin is within normal operating range.
Section 2: Operating Modes
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Page 5
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet 68HC05C5.PDF ] |
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