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PDF CY7C68034 Data sheet ( Hoja de datos )
| Número de pieza | CY7C68034 | |
| Descripción | EZ-USB NX2LP-Flex Flexible USB NAND Flash Controller | |
| Fabricantes | Cypress Semiconductor | |
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CY7C68033/CY7C68034
EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller
CY7C68033/CY7C68034 Silicon Features
• Certified compliant for Bus- or Self-powered USB 2.0
operation (TID# 40490118)
• Single-chip, integrated USB 2.0 transceiver and smart SIE
• Ultra low power – 43 mA typical current draw in any mode
• Enhanced 8051 core
— Firmware runs from internal RAM, which is downloaded
from NAND flash at startup
— No external EEPROM required
• 15 KBytes of on-chip Code/Data RAM
— Default NAND firmware ~8 kB
— Default free space ~7 kB
• Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• SmartMedia Standard Hardware ECC generation with 1-bit
correction and 2-bit detection
• GPIF (General Programmable Interface)
— Allows direct connection to most parallel interfaces
— Programmable waveform descriptors and configuration
registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
• 12 fully-programmable GPIO pins
• Integrated, industry-standard enhanced 8051
— 48-MHz, 24-MHz, or 12-MHz CPU operation
— Four clocks per instruction cycle
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 3.3V operation with 5V tolerant inputs
• Vectored USB interrupts and GPIF/FIFO interrupts
• Separate data buffers for the Set-up and Data portions of a
CONTROL transfer
• Integrated I2C™ controller, runs at 100 or 400 kHz
• Four integrated FIFOs
— Integrated glue logic and FIFOs lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— Uses external clock or asynchronous strobes
— Easy interface to ASIC and DSP ICs
• Available in space saving, 56-pin QFN package
CY7C68034 Only Silicon Features:
• Ideal for battery powered applications
— Suspend current: 100 μA (typ.)
CY7C68033 Only Silicon Features:
• Ideal for non-battery powered applications
— Suspend current: 300 μA (typ.)
Block Diagram
24 MHz
Ext. Xtal
NX2LP-Flex
High-performance,
enhanced 8051 core
with low power options
Connected for
full-speed USB
/0.5
x20 /1.0
PLL /2.0
VCC
1.5k
8051 Core
12/24/48 MHz,
four clocks/cycle
NAND
Boot Logic
(ROM)
D+
D–
Integrated full- and
high-speed XCVR
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
15 kB
RAM
I2C
Master
Additional I/Os
ECC
GPIF
RDY (2)
CTL (3)
4 kB
FIFO
8/16
General Programmable
I/F to ASIC/DSP or bus
standards such as 8-bit
NAND, EPP, etc.
Up to 96 MB/s burst rate
Enhanced USB core
simplifies 8051 code
‘Soft Configuration’ enables
easy firmware changes
FIFO and USB endpoint memory
(master or slave modes)
Cypress Semiconductor Corporation
Document #: 001-04247 Rev. *D
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised September 21, 2006
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CY7C6803w3w/wC.DYat7aSChe6et84U0.c3o4m
Figure 4. NX2LP-Flex Enumeration Sequence
Start-up
Yes NAND Flash
Present?
No
values stored in ROM space. The default silicon ID values
should only be used for development purposes. Cypress
requires designers to use their own Vendor ID for final
products. A Vendor ID is obtained through registration with the
USB Implementor’s Forum (USB-IF). Also, if the NX2LP-Flex
is used as a mass storage class device, a unique USB serial
number is required for each device in order to comply with the
USB Mass Storage class specification.
Cypress provides all the software tools and drivers necessary
for properly programming and testing the NX2LP-Flex. Please
refer to the documentation in the development kit for more
information on these topics.
NAND Flash
Programmed?
Yes
No
Table 2. Default Silicon ID Values
Vendor ID
Product ID
Device release
Default VID/PID/DID
0x04B4 Cypress Semiconductor
0x8613 EZ-USB® Default
0xAnnn Depends on chip revision
(nnn = chip revision, where first
silicon = 001)
Load Firmware
From NAND
Load Default
Descriptors and
Configuration Data
Enumerate
According To
Firmware
Enumerate As
Unprogrammed
NX2LP-Flex
Normal Operation
Mode
Manufacturing
Mode
Normal Operation Mode
In Normal Operation Mode, the NX2LP-Flex behaves as a
USB 2.0 Mass Storage Class NAND Flash controller. This
includes all typical USB device states (powered, configured,
etc.). The USB descriptors are returned according to the data
stored in the configuration data memory area. Normal read
and write access to the NAND Flash is available in this mode.
Manufacturing Mode
In Manufacturing Mode, the NX2LP-Flex enumerates using
the default descriptors and configuration data that are stored
in internal ROM space. This mode allows for first-time
programming of the configuration data memory area, as well
as board-level manufacturing tests.
Default Silicon ID Values
To facilitate proper USB enumeration when no programmed
NAND Flash is present, the NX2LP-Flex has default silicon ID
ReNumeration™
Cypress’s ReNumeration™ feature is used in conjunction with
the NX2LP-Flex manufacturing software tools to enable
first-time NAND programming. It is only available when used
in conjunction with the NX2LP-Flex Manufacturing tools, and
is not enabled during normal operation.
Bus-powered Applications
The NX2LP-Flex fully supports bus-powered designs by
enumerating with less than 100 mA, as required by the USB
2.0 specification.
Interrupt System
INT2 Interrupt Request and Enable Registers
NX2LP-Flex implements an autovector feature for INT2 and
INT4. There are 27 INT2 (USB) vectors, and 14 INT4
(FIFO/GPIF) vectors. See the EZ-USB Technical Reference
Manual (TRM) for more details.
USB-Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that normally would be
required to identify the individual USB interrupt source, the
NX2LP-Flex provides a second level of interrupt vectoring,
called Autovectoring. When a USB interrupt is asserted, the
NX2LP-Flex pushes the program counter onto its stack then
jumps to address 0x0500, where it expects to find a ‘jump’
instruction to the USB Interrupt service routine.
Developers familiar with Cypress’s programmable USB
devices should note that these interrupt vector values differ
from those used in other EZ-USB microcontrollers. This is due
to the additional NAND boot logic that is present in the
NX2LP-Flex ROM space. Also, these values are fixed and
cannot be changed in the firmware.
Document #: 001-04247 Rev. *D
Page 5 of 33
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the default NAND firmware image implements an 8-bit data
bus and up to 8 chip enable pins on the GPIF ports, it is recom-
mended that designs based upon the default firmware image
use an 8-bit data bus as well.
Each GPIF vector defines the state of the control outputs, and
determines what state a ready input (or multiple inputs) must
be before proceeding. The GPIF vector can be programmed
to advance a FIFO to the next data value, advance an address,
etc. A sequence of the GPIF vectors make up a single
waveform that will be executed to perform the desired data
move between the NX2LP-Flex and the external device.
Three Control OUT Signals
The NX2LP-Flex exposes three control signals, CTL[2:0].
CTLx waveform edges can be programmed to make transi-
tions as fast as once per clock (20.8 ns using a 48-MHz clock).
Two Ready IN Signals
The 8051 programs the GPIF unit to test the RDY pins for
GPIF branching. The 56-pin package brings out two signals,
RDY[1:0].
Long Transfer Mode
In GPIF Master mode, the 8051 appropriately sets GPIF trans-
action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 232 transactions.
The GPIF automatically throttles data flow to prevent under- or
over-flow until the full number of requested transactions
complete. The GPIF decrements the value in these registers
to represent the current status of the transaction.
ECC Generation[5]
The NX2LP-Flex can calculate ECCs (Error-Correcting
Codes) on data that passes across its GPIF or Slave FIFO
interfaces. There are two ECC configurations:
• Two ECCs, each calculated over 256 bytes (SmartMedia
Standard)
• One ECC calculated over 512 bytes.
The two ECC configurations described below are selected by
the ECCM bit. The ECC can correct any one-bit error or detect
any two-bit error.
ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of
data. This configuration conforms to the SmartMedia Standard
and is used by both the NAND boot logic and default NAND
firmware image.
When any value is written to ECCRESET and data is then
passed across the GPIF or Slave FIFO interface, the ECC for
the first 256 bytes of data will be calculated and stored in
ECC1. The ECC for the next 256 bytes of data will be stored
in ECC2. After the second ECC is calculated, the values in the
ECCx registers will not change until ECCRESET is written
again, even if more data is subsequently passed across the
interface.
ECCM = 1
One 3-byte ECC calculated over a 512-byte block of data.
When any value is written to ECCRESET and data is then
passed across the GPIF or Slave FIFO interface, the ECC for
the first 512 bytes of data will be calculated and stored in
ECC1; ECC2 is unused. After the ECC is calculated, the value
in ECC1 will not change until ECCRESET is written again,
even if more data is subsequently passed across the interface
Autopointer Access
NX2LP-Flex provides two identical autopointers. They are
similar to the internal 8051 data pointers, but with an additional
feature: they can optionally increment after every memory
access. Also, the autopointers can point to any NX2LP-Flex
register or endpoint buffer space.
I2C Controller
NX2LP has one I2C port that the 8051, once running uses to
control external I2C devices. The I2C port operates in master
mode only. The I2C post is disabled at startup and only
available for use after the initial NAND access.
I2C Port Pins
The I2C pins SCL and SDA must have external 2.2-kΩ pull-up
resistors even if no EEPROM is connected to the NX2LP.
I2C Interface General-Purpose Access
The 8051 can control peripherals connected to the I2C bus
using the I2CTL and I2DATA registers. NX2LP provides I2C
master control only and is never an I2C slave.
Note
5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
Document #: 001-04247 Rev. *D
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| PDF Descargar | [ Datasheet CY7C68034.PDF ] | |
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