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CY7C68024 PDF даташит

Спецификация CY7C68024 изготовлена ​​​​«Cypress Semiconductor» и имеет функцию, называемую «EZ-USB NX2LP USB 2.0 NAND Flash Controller».

Детали детали

Номер произв CY7C68024
Описание EZ-USB NX2LP USB 2.0 NAND Flash Controller
Производители Cypress Semiconductor
логотип Cypress Semiconductor логотип 

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CY7C68024 Даташит, Описание, Даташиты
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CY7C68023/CY7C68024
EZ-USB NX2LP™ USB 2.0 NAND Flash Controller
1.0 Features
• High (480-Mbps) or full (12-Mbps) speed USB support
• Both common NAND page sizes supported
— 512bytes –Up to 1Gbit Capacity
— 2K bytes –Up to 8Gbit Capacity
• 8 chip enable pins
— Up to 8 NAND Flash single-device chips
— Up to 4 NAND Flash dual-device chips
• Industry standard ECC NAND Flash correction
— 1-bit per 256 correction
— 2-bit error detection
• Industry standard (SmartMedia) page management for
wear leveling algorithm, bad block handling, and Physical
to Logical management.
• Supports 8-bit NAND Flash interfaces
• Supports 30ns, 50ns, 100ns NAND Flash timing
• Complies with USB Mass Storage Class Specification rev
1.0
• CY7C68024 complies with USB 2.0 Specification for Bus-
Powered Devices (TID# 40460274)
• 43-mA Typical Active Current
• Space-saving and lead-free 56-QFN package (8mm ×
8mm)
• Support for board-level manufacturing test via USB
interface
• 3.3V NAND Flash operation
NAND Flash power management support
2.0 Introduction
The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND
Flash controller. This controller adheres to the Mass Storage
Class Bulk-Only Transport Specification. The USB port of the
NX2LP is connected to a host computer directly or via the
downstream port of a USB hub. Host software issues
commands and data to the NX2LP and receives status and
data from the NX2LP using standard USB protocol.
The NX2LP supports industry leading 8-bit NAND Flash inter-
faces and both common NAND page sizes of 512 and 2k
bytes. Eight chip enable pins allow the NX2LP to be connected
to up to eight single- or four dual-device NAND Flash chips.
Certain NX2LP features are configurable, enabling the NX2LP
to meet the needs of different designs’ requirements.
24 MHz
Xtal
Chip Reset
PLL
VBUS
D+
D-
USB 2.0
Xceiver
EZ-USB NX2LP
Internal Control Logic
Control
Write Protect
LED2#
LED1#
NAND Control Signals
NAND Flash
Interface
Logic
Chip Enable Signals
Smart HS/
FS USB
Engine
Data
Figure 1-1. NX2LP Block Diagram
8-bit Data Bus
Cypress Semiconductor Corporation
Document #: 38-08055 Rev. *A
• 3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised March 16, 2005









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CY7C68024 Даташит, Описание, Даташиты
3.0 Pin Assignments
3.1 Pin Diagram
CY7C680w2w3w/.CDaYta7ShCee6t48U.0co2m4
R_B1# 1
R_B2# 2
AVCC 3
XTALOUT 4
XTALIN 5
AGND 6
AVCC 7
DPLUS 8
DMINUS 9
AGND 10
VCC 11
GND 12
N/C 13
GND 14
EZ-USB NX2LP
56-pin QFN
42 RESET#
41 GND
40 N/C
39 N/C
38 WP_SW#
37 WP_NF#
36 LED2#
35 LED1#
34 ALE
33 CLE
32 VCC
31 RE1#
30 RE0#
29 WE#
Figure 3-1. 56-pin QFN
3.2 Pin Descriptions
Pin Name Type
1 R_B1#[1]
I
Default State at Start-up
Description
Z Ready/Busy 1 (2.2k to 4k pull-up resistor is required)
2 R_B2#
I
Z Ready/Busy 2 (2.2k to 4k pull-up resistor is required)
3 AVCC PWR
PWR
Analog 3.3V supply
4 XTALOUT Xtal
N/A Crystal output
5 XTALIN Xtal
N/A Crystal input
6 AGND GND
GND
Ground
7 AVCC PWR
PWR
Analog 3.3V supply
8 DPLUS I/O
Z USB D+
9 DMINUS I/O
Z USB D-
10 AGND GND
GND
Ground
11 VCC PWR
PWR
3.3V supply
12 GND GND
GND
Ground
13 N/C N/A
N/A No connect
14 GND GND
GND
Ground
Note:
1. A # sign after the pin name indicates that it is an active LOW signal.
Document #: 38-08055 Rev. *A
Page 2 of 9









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CY7C68024 Даташит, Описание, Даташиты
CY7C680w2w3w/.CDaYta7ShCee6t48U0.co2m4
3.2 Pin Descriptions (continued)
Pin Name Type
15 Reserved N/A
16 Reserved N/A
17 VCC PWR
18 DDO
I/O
19 DD1
I/O
20 DD2
I/O
21 DD3
I/O
22 DD4
I/O
23 DD5
I/O
24 DD6
I/O
25 DD7
I/O
26 GND GND
27 VCC PWR
28 GND GND
29 WE#
O
30 RE0#
O
31 RE1#
O
32 VCC PWR
33 CLE
O
34 ALE
O
35 LED1#
O
36 LED2#
O
37 WP_NF# O
38 WP_SW# I
39 N/C N/A
40 N/C N/A
41 GND GND
42 RESET#
I
43 VCC PWR
44 Reserved N/A
45 CE0#
O
46 CE1#
O
47 CE2#
O
48 CE3#
O
49 CE4#
O
50 CE5#
O
51 CE6#
O
52 CE7#
O
53 GND GND
54 N/C N/A
55 VCC PWR
56 GND GND
Default State at Start-up
N/A
N/A
PWR
Z
Z
Z
Z
Z
Z
Z
Z
GND
PWR
GND
H
H
H
PWR
Z
Z
Z
Z
Z
Z
N/A
N/A
GND
Z
PWR
N/A
Z
Z
Z
Z
Z
Z
Z
Z
GND
N/A
PWR
GND
Description
Must be tied HIGH (no pull-up resistor required)
Must be tied HIGH (no pull-up resistor required)
3.3V supply
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Ground
3.3V supply
Ground
Write enable
Read Enable 0
Read Enable 1
3.3V supply
Command latch enable
Address latch enable
Data activity LED sink
Chip active LED sink
Write-protect NAND Flash
Write-protect switch input
No connect
No connect
Ground
NX2LP chip reset
3.3V supply
Must be tied HIGH
Chip enable 0
Chip enable 1
Chip enable 2
Chip enable 3
Chip enable 4
Chip enable 5
Chip enable 6
Chip enable 7
Ground
No connect
3.3V supply
Ground
Document #: 38-08055 Rev. *A
Page 3 of 9










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Cypress Semiconductor

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