|
|
PDF HD61202U Data sheet ( Hoja de datos )
| Número de pieza | HD61202U | |
| Descripción | Dot Matrix Liquid Crystal GraphicDisplay Column Driver | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HD61202U (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
HD61202U
(Dot Matrix Liquid Crystal GraphicDisplay Column Driver)
Description
HD61202U is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores
the display data transferred from a 8-bit micro controller in the internal display RAM and generates dot
matrix liquid crystal driving signals.
Each bit data of display RAM corresponds to on/off state of a dot of a liquid crystal display to provide
more flexible than character display.
As it is internally equipped with 64 output drivers for display, it is available for liquid crystal graphic
displays with many dots.
The HD61202U, which is produced in the CMOS process, can complete portable battery drive equipment
in combination with a CMOS micro-controller, utilizing the liquid crystal display’s low power
dissipation.
Moreover it can facilitate dot matrix liquid crystal graphic display system configuration in combination
with the row (common) driver HD61203U.
Features
• Dot matrix liquid crystal graphic display column driver incorporating display RAM
• RAM data direct display by internal display RAM
RAM bit data 1: On
RAM bit data 0: Off
• Internal display RAM address counter preset, increment
• Display RAM capacity: 512 bytes (4096 bits)
• 8-bit parallel interface
• Internal liquid crystal display driver circuit: 64
• Display duty cycle
Drives liquid crystal panels with 1/32–1/64 duty cycle multiplexing
816
1 page  
HD61202U
HCD61202U PAD Arrangement
www.DataSheet4U.com
No.1
NO.3
NO.27
CHIP CODE
HD61202U
NO.78
NO.54
Chip Size
Coordinate
Origin
Pad Size
: 4.08 × 4.08 mm2
: Pad Center
: Chip center
: 90 × 90 µm2
No.28
No.53
HCD61202U Pad Location Coordinates
PAD PAD Coordinate PAD PAD Coordinate
No. Name X
Y
No. Name X
Y
1 ADC –1493 1756
2 M –1649 1756
3 VCC –1789 1689
4 V4R –1789 1445
5 V3R –1789 1293
6 V2R –1789 1148
7 V1R –1789 1011
8 VEE2 –1789 869
9 Y64 –1789 721
10 Y63 –1789 591
11 Y62 –1789 461
12 Y61 –1789 331
13 Y60 –1789 201
14 Y59 –1789 71
15 Y58 –1789 –60
16 Y57 –1789 –190
17 Y56 –1789 –320
18 Y55 –1789 –450
19 Y54 –1789 –580
20 Y53 –1789 –710
21 Y52 –1789 –840
22 Y51 –1789 –970
23 Y50 –1789 –1100
24 Y49 –1789 –1230
25 Y48 –1789 –1369
26 Y47
27 Y46
28 Y45
29 Y44
30 Y43
31 Y42
32 Y41
33 Y40
34 Y39
35 Y38
36 Y37
37 Y36
38 Y35
39 Y34
40 Y33
41 Y32
42 Y31
43 Y30
44 Y29
45 Y28
46 Y27
47 Y26
48 Y25
49 Y24
50 Y23
–1789 –1508
–1789 –1653
–1764 –1789
–1604 –1789
–1452 –1789
–1312 –1789
–1171 –1789
–976 –1789
–846 –1789
–716 –1789
–586 –1789
–456 –1789
–326 –1789
–196 –1789
–65 –1789
65 –1789
195 –1789
325 –1789
455 –1789
585 –1789
715 –1789
845 –1789
975 –1789
1170 –1789
1311 –1789
PAD PAD Coordinate
No. Name X Y
51 Y22
52 Y21
53 Y20
54 Y19
55 Y18
56 Y17
57 Y16
58 Y15
59 Y14
60 Y13
61 Y12
62 Y11
63 Y10
64 Y9
65 Y8
66 Y7
67 Y6
68 Y5
69 Y4
70 Y3
71 Y2
72 Y1
73 VEE1
74 V1L
75 V2L
1452 –1789
1604 –1789
1764 –1789
1789 –1654
1789 –1507
1789 –1369
1789 –1230
1789 –1100
1789 –970
1789 –840
1789 –710
1789 –580
1789 –450
1789 –320
1789 –190
1789 –60
1789 71
1789 201
1789 331
1789 461
1789 591
1789 721
1789 1024
1789 1153
1789 1293
PAD PAD Coordinate
No. Name X
Y
76 V3L 1789 1442
77 V4L 1789 1590
78 GND 1789 1756
79 DB0 1495 1756
80 DB1 1335 1756
81 DB2 1176 1756
82 DB3
83 DB4
84 DB5
85 DB6
86 DB7
1016
854
694
535
375
1756
1756
1756
1756
1756
87 NC
88 NC
89 NC
90 CS3
218 1756
91 CS2
62 1756
92 CS1 –94 1756
93 RST –249 1756
94 R/W –405 1756
95 D/I
96 CL
97 ø2
–560
–716
–871
1756
1756
1756
98 ø1 –1027 1756
99 E –1182 1756
100 FRM –1338 1756
820
5 Page 
HD61202U
www.DataSheet4U.com
Display On/Off Flip/Flop
The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64. In on
state, the display data corresponding to that in RAM is output to the segments. On the other hand, the
display data at all segments disappear in off state independent of the data in RAM. It is controlled by
display on/off instruction. #$% signal = 0 sets the segments in off state. The status of the flip/flop is
output to DB5 by status read instruction. Display on/off instruction does not influence data in RAM. To
control display data latch by this flip/flop, CL signal (display synchronous signal) should be input
correctly.
Display Start Line Register
The display start line register specifies the line in RAM which corresponds to the top line of LCD panel,
when displaying contents in display data RAM on the LCD panel. It is used for scrolling of the screen.
6-bit display start line information is written into this register by the display start line set instruction.
When high level of the FRM signal starts the display, the information in this register is transferred to the
Z address counter, which controls the display address, presetting the Z address counter.
X, Y Address Counter
A 9-bit counter which designates addresses of the internal display data RAM. X address counter (upper 3
bits) and Y address counter (lower 6 bits) should be set to each address by the respective instructions.
1. X address counter
Ordinary register with no count functions. An address is set by instruction.
2. Y address counter
An Address is set by instruction and is increased by 1 automatically by R/W operations of display
data. The Y address counter loops the values of 0 to 63 to count.
Display Data RAM
Stores dot data for display. 1-bit data of this RAM corresponds to light on (data = 1) and light off (data =
0) of 1 dot in the display panel. The correspondence between Y addresses of RAM and segment pins can
be reversed by ADC signal.
As the ADC signal controls the Y address counter, reversing of the signal during the operation causes
malfunction and destruction of the contents of register and data of RAM. Therefore, never fail to connect
ADC pin to VCC or GND when using.
Figure 3 shows the relations between Y address of RAM and segment pins in the cases of ADC = 1 and
ADC = 0 (display start line = 0, 1/64 duty cycle).
826
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD61202U.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD61202U | Dot Matrix Liquid Crystal GraphicDisplay Column Driver | Hitachi Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |