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PDF 28C16B Data sheet ( Hoja de datos )
| Número de pieza | 28C16B | |
| Descripción | M28C16B | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M28C16B
M28C17B
16 Kbit (2K x 8) Parallel EEPROM
With Software Data Protection
PRELIMINARY DATA
s Fast Access Time: 90 ns at VCC=5V
s Single Supply Voltage:
– 4.5 V to 5.5 V for M28CxxB
– 2.7 V to 3.6 V for M28CxxB-W
s Low Power Consumption
s Fast BYTE and PAGE WRITE (up to 64 Bytes)
– 3 ms at VCC=4.5 V
– 5 ms at VCC=2.7 V
s Enhanced Write Detection and Monitoring:
– Data Polling
– Toggle Bit
– Page Load Timer Status
s JEDEC Approved Bytewide Pin-Out
s Software Data Protection
s 100000 Erase/Write Cycles (minimum)
s Data Retention (minimum): 40 Years
DESCRIPTION
The M28C16B and M28C17B devices consist of
2048x8 bits of low power, parallel EEPROM, fabri-
cated with STMicroelectronics’ proprietary single
polysilicon CMOS technology. The devices offer
fast access time, with low power dissipation, and
require a single voltage supply.
Table 1. Signal Names
A0-A10
Address Input
DQ0-DQ7
Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready/Busy (M28C17B only)
VCC
Supply Voltage
VSS Ground
PLCC32 (K)
Figure 1. Logic Diagram
VCC
11
A0-A10
8
DQ0-DQ7
W M28C16B
M28C17B
E
RB
G (M28C17B only)
VSS
AI02816
February 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/17
1 page  
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M28C16B, M28C17B
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Page Write
Timing
(see note 1)
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write A0h in
Address 555h
SDP is set
Page Write
Timing
(see note 1)
Physical
Page Write
Instruction
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write A0h in
Address 555h
Page Write
(1 up to 64 bytes)
Write
is Enabled
SDP Enable Algorithm
Write to Memory
When SDP is SET
AI02819
Note: 1. The most significant address bits (A10 to A6) differ during these specific Page Write operations.
ignored, and have no effect on the memory con-
tents.
The device remains in this mode until a valid Soft-
ware Data Protection disable sequence is re-
ceived. The device reverts to its “unprotected”
state.
The status of the Software Data Protection (en-
abled or disabled) is represented by a non-volatile
latch, and is remembered across periods of the
power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,
the user has to write specific data bytes into six dif-
Figure 5. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
ferent locations, as shown in Figure 6. This com-
plex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
Figure 6. Software Data Protection Disable
Algorithm
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Page Write
Timing
Write 80h in
Address 555h
Write AAh in
Address 555h
Write 55h in
Address 2AAh
DP
TB
PLTS
Hi-Z
= Data Polling
= Toggle Bit
= Page Load Timer Status
= High impedance
AI02815
Write 20h in
Address 555h
Unprotected State
AI02820
5/17
5 Page 
Table 10B. Write Mode AC Characteristics for M28CxxB-W (3V range)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol Alt.
Parameter
Test Condition
tAVWL tAS Address Valid to Write Enable Low
tAVEL tAS Address Valid to Chip Enable Low
tELWL tCES Chip Enable Low to Write Enable Low
tGHWL tOES Output Enable High to Write Enable Low
tGHEL tOES Output Enable High to Chip Enable Low
tWLEL tWES Write Enable Low to Chip Enable Low
tWLAX tAH Write Enable Low to Address Transition
tELAX tAH Chip Enable Low to Address Transition
tWLDV tDV Write Enable Low to Input Valid
tELDV tDV Chip Enable Low to Input Valid
tELEH tWP Chip Enable Low to Chip Enable High
tWHEH tCEH Write Enable High to Chip Enable High
tWHGL tOEH Write Enable High to Output Enable Low
tEHGL tOEH Chip Enable High to Output Enable Low
tEHWH tWEH Chip Enable High to Write Enable High
tWHDX tDH Write Enable High to Input Transition
tEHDX tDH Chip Enable High to Input Transition
tWHWL tWPH Write Enable High to Write Enable Low
tWLWH tWP Write Enable Low to Write Enable High
tWLQ5H tBLC Time-out after the last byte write
tQ5HQ5X tWC Write Cycle Time
tDVWH tDS Data Valid before Write Enable High
tDVEH tDS Data Valid before Chip Enable High
E = VIL, G = VIH
G = VIH, W = VIL
G = VIH
E = VIL
W = VIL
G = VIH
E = VIL, G = VIH
G = VIH, W = VIL
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M28C16B, M28C17B
M28C17B-xxW
Min Max
0
0
0
0
0
0
100
100
1
1
100 1000
0
0
0
0
0
0
50 1000
100
100
5
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ns
ns
11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet 28C16B.PDF ] | |
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