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PDF AS8202NF Data sheet ( Hoja de datos )
| Número de pieza | AS8202NF | |
| Descripción | TTP-C2NF Communication Controller | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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AS8202NF
TTP-C2NF Communication Controller
Data Sheet
1 General Description
The AS8202NF communication controller is an
integrated device supporting serial communication
according to the TTP specification version 1.1. It
performs all communication tasks such as reception and
transmission of messages in a TTP cluster without
interaction of the host CPU. TTP provides mechanisms
that allow the deployment in high-dependability
distributed real-time systems. It provides the following
services:
Predictable transmission of messages with minimal
jitter
Fault-tolerant distributed clock synchronization
Consistent membership service with small delay
Masking of single faults
2 Key Features
Dual-channel controller for redundant data transfers
Dedicated controller supporting TTP (time-triggered
protocol class C)
Suited for dependable distributed real-time systems
with guaranteed response time
Asynchronous data rate up to 5 Mbit/s (MFM/
Manchester)
Synchronous data rate 5 to 25 Mbit/s
Bus interface (speed, encoding) for each channel
selectable independently
Figure 1. Block Diagram
40 MHz main clock with support for 10 MHz crystal,
10 MHz oscillator or 40 MHz oscillator
16 MHz bus guardian clock with support for 16 MHz
crystal or 16 MHz oscillator
Single power supply 3.3V, 0.35µm CMOS process
Full automotive temperature range (-40ºC to 125ºC)
16k x 16 SRAM for message, status, control area
(communication network interface) and for
scheduling information (MEDL)
4k x 16 (plus parity) instruction code RAM for
protocol execution code
Data sheet conforms to protocol revision 2.04
16k x 16 instruction code ROM containing startup
execution code and deprecated protocol code
revision 1.00
16 Bit non-multiplexed asynchronous host CPU
interface
16 Bit RISC architecture
Software tools, design support, development boards
available (www.tttech.com)
Certification support package according to RTCA/
DO-254 DAL A available (www.tttech.com)
80 pin LQFP80 Package
3 Applications
Application fields: automotive (by-wire braking, steering,
vehicle dynamics control, drive train control), aerospace
(aircraft electronic systems), industrial systems, railway
systems.
D[15:0]
Host
A[11:0]
Processor
Interface
CEB
OEB
WEB
READYB
INTB
LED[2:0]
RAM_CLK_TESTSE
USE_RAM_CLK
AS8202NF
Communication
network
interface
(CNI)
TTP
Protocol
processor core
Receiver
Bus guardian
Transmitter
RxD[1:0]
RXCLK[1:0]
RxDV[1:0]
RXER[1:0]
XIN1
XOUT1
TTP Bus
Media
Drivers
TxD[1:0]
CTS[1:0]
TxCLK[1:0]
Quartz or
Oscillator
XIN0
XOUT0
PLLOFF
RESETB
Instruction
memory
RAM & ROM
Test
Interface
RAM_CLK_TESTSE
FTEST
STEST
Test
FIDIS
Interface
TTEST
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Revision 2.1
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1 page  
AS8202NF TTP-C2NF
Data Sheet - Pin Assignments
Table 2. Pin Directions
Dir
OPD
A
P
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Description
TTL Output with Internal Weak Pull-Down at Tristate
Analog CMOS Pin
Power Pin
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TTTech Computertechnik AG
Revision 2.1
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5 Page 
AS8202NF TTP-C2NF
Data Sheet - Detailed Description
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Table 6. Asynchronous DPRAM interface
Symbol
Parameter
Conditions
Min
14
RAM_CLK_TESTSE
Rising to READYB Rising
USE_RAM_CLK=1
3
Ready
delay='00'
3.6
15
RAM_CLK_TESTSE
Rising to READYB
Deactivated 1->Z
USE_RAM_CLK
=1
Ready
delay=01
Ready
delay=10
4.5
5.4
Ready
delay=11
6.4
Read to Read Access
16 Inactivity Time (CEB, OEB min = 1.5 Tc
low to CEB, OEB low)
37.51
Read to Write Access
17 Inactivity Time (CEB, OEB
low to CEB, WEB low)
51
Write to Write Access
18 Inactivity Time (CEB, WEB
low to CEB, WEB low)
51,2
Write to Read Access
19 Inactivity Time (CEB, WEB
low to CEB, OEB low)
51,2
Typ
Max Units
9.7 ns
12.9
15.4
ns
18.8
22.2
ns
ns
ns
ns
1. Prior to starting a read or write access, CEB, WEB and OEB have to be stable for at least 5 ns (see symbol 3, 4,
8, 9). In addition the designer has to consider the minimum inactivity time according to symbols 16, 17, 18, 19.
For more information on the inactivity times (see Figure 3).
2. To allow proper internal initialization, after finishing any write access (CEB or WEB is high) to the internal
CONTROLLER_ON register, CEB OEB and WEB have to be stable high within 200 ns (min = 8 Tc).
Note: All values not tested during production, guaranteed by design.
Figure 3. Read/Write Access Inactivity Time
16 17 18 19
Read
Read
Write
Write
Read
CEB
OEB
WEB
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