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PDF STP16CPPS05 Data sheet ( Hoja de datos )
| Número de pieza | STP16CPPS05 | |
| Descripción | Low voltage 16-bit constant current LED sink driver | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STP16CPPS05
Low voltage 16-bit constant current
LED sink driver with auto power-saving
Preliminary data
Features
■ Low voltage power supply down to 3 V
■ 16 constant current output channels
■ Adjustable output current through external
resistor
■ Serial data IN/parallel data OUT
■ Auto power-saving
■ 3.3 V MCU-driving capability
■ Output current: 3 to 40 mA
■ 30 MHz clock frequency
■ Available in high thermal efficiency TSSOP
exposed pad
■ ESD protection: 2 kV HBM, 200 V MM
Description
The STP16CPPS05 is a monolithic, low voltage,
low current power 16-bit shift register designed for
LED panel displays. The device features a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the output stage,
sixteen regulated current sources are designed to
www.DataSphreoevt4idUe.c3omto 40 mA of constant current to drive the
LEDs.
Table 1. Device summary
QSOP-24
SO-24
TSSOP24
TSSOP24
(exposed pad)
The STP16CPPS05 output current can be
adjusted through an external resistor to control
the light intensity of the LEDs.
LED brightness is adjustable from 0% to 100% via
the OE pin.
The auto power-shutdown and auto power-ON
feature allows the device to save power with no
external intervention.
The STP16CPPS05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high 30 MHz clock frequency
makes the device suitable for high data rate
transmission. The 3.3 V supply is well suited for
applications which interface a 3.3 V MCU.
Compared to a standard TSSOP package, the
TSSOP with exposed pad increases heat
dissipation capability by a factor of 2.5
Order codes
Package
Packaging
STP16CPPS05MTR
STP16CPPS05TTR
STP16CPPS05XTTR
STP16CPPS05PTR
SO-24
TSSOP24
TSSOP24 exposed pad
QSOP-24
1000 parts per reel
2500 parts per reel
2500 parts per reel
2500 parts per reel
October 2009
Doc ID 16536 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/29
www.st.com
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1 page  
STP16CPPS05
2 Electrical ratings
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other condition above those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol
Parameter
VDD Supply voltage
VO Output voltage
IO Output current
VI Input voltage
IGND GND terminal current
fCLK Clock frequency
TJ Junction temperature range (1)
1. Such absolute value is based on the thermal shutdown protection.
Value
0 to 7
-0.5 to 20
50
-0.4 to VDD
800
50
-40 to +170
Unit
V
V
mA
V
mA
MHz
°C
2.2 Thermal data
Table 5. Thermal data
Symbol
Parameter
Value
www.DataSheet4U.com
TA
TJ-OPR
TSTG
RthJA
Operating free-air temperature range
Operating thermal junction temperature range
Storage temperature range
SO-24
Thermal resistance junction-
ambient (1)
TSSOP24
TSSOP24(2)
Exposed Pad
QSOP-24
-40 to +125
-40 to +150
-55 to +150
42.7
55
37.5
55
1. According with JEDEC standard 51-7B
2. The exposed pad should be soldered directly to the PCB to obtain the thermal benefits.
Unit
°C
°C
°C
°C/W
°C/W
°C/W
°C/W
Doc ID 16536 Rev 1
5/29
5 Page 
STP16CPPS05
5 Timing diagrams
Timing diagrams
Note:
Table 9.
CLOCK
Truth table
LE OE
HL
LL
HL
XL
XH
SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO
Dn
Dn + 1
Dn + 2
Dn + 3
Dn + 3
Dn ..... Dn - 7 ..... Dn -15
No change
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn + 2 ..... Dn - 5 ..... Dn -13
OFF
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L
Figure 7. Timing diagram
www.DataSheet4U.com
Note: 1 Latch and output enable terminals are level-sensitive and are not synchronized with rising or
falling edge of CLK signal.
2 When LE terminal is low level, the latch circuit holds previous set of data.
3 When LE terminal is high level, the latch circuit refreshes new set of data from SDI chain.
4 When OE terminal is at low level, the output terminals Out 0 to Out 15 respond to data in the
latch circuits, either ‘1’ for ON or ‘0’ for OFF.
5 When OE terminal is at high level, all output terminals are switched OFF.
Doc ID 16536 Rev 1
11/29
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