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PDF AD9575 Data sheet ( Hoja de datos )
| Número de pieza | AD9575 | |
| Descripción | NETWORK CLOCK GENERATOR | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Network Clock Generator, Two Outputs
AD9575
FEATURES
Fully integrated VCO/PLL core
0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz
0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz
0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz
Input crystal frequency of 19.44 MHz, 25 MHz, or
25.78125 MHz
Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,
100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,
159.375 MHz, 161.13 MHz, and 312.5 MHz outputs
LVDS/LVPECL/LVCMOS output format
Integrated loop filter
Space saving 4.4 mm × 5.0 mm TSSOP
100 mW power dissipation (LVDS output)
120 mW power dissipation (LVPECL output)
3.3 V operation
APPLICATIONS
GbE/FC/SONET line cards, switches, and routers
CPU/PCI-e applications
Low jitter, low phase noise clock generation
GENERAL DESCRIPTION
The AD9575 provides a highly integrated, dual output clock
generator function including an on-chip PLL core that is
optimized for network clocking. The integer-N PLL design is
based on the Analog Devices, Inc., proven portfolio of high
performance, low jitter frequency synthesizers to maximize line
card performance. Other applications with demanding phase
noise and jitter requirements also benefit from this part.
The PLL section consists of a low noise phase frequency detector
(PFD), a precision charge pump, a low phase noise voltage
controlled oscillator (VCO), and pin selectable feedback and
output dividers.
By connecting an external crystal, popular network output
frequencies can be locked to the input reference. The output
divider and feedback divider ratios are pin programmable for the
required output rates. No external loop filter components are
required, thus conserving valuable design time and board space.
The AD9575 is available in a 16-lead, 4.4 mm × 5.0 mm TSSOP
and can be operated from a single 3.3 V supply. The temperature
range is −40°C to +85°C.
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FUNCTIONAL BLOCK DIAGRAM
VDD × 5
XTAL
OSC
AD9575
LDO
VCO
LVDS OR
LVPECL
LVCMOS
SEL
100MHz
TO 312.5MHz
33.33MHz/
62.5MHz/SEL1
GND × 5
Figure 1.
SEL0
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9575
OUTPUT FREQUENCY SELECT
Typical (typ) value is given for VS = 3.3 V, TA = 25°C, unless otherwise noted
Table 4.
Parameter
Select Pins (SEL0/SEL1)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Min
0.83 × VS + 0.2
Typ
Max Unit
0.33 × VS − 0.2
190
150
V
V
μA
μA
Test Conditions/Comments
Pull-down to GND, pull-up to VDD, pull-up to VDD via 15 kΩ,
do not connect
CLOCK OUTPUTS
Typical (typ) value is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter
LVDS CLOCK OUTPUT
Output Frequency
Differential Output Voltage (VOD)
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
Duty Cycle
LVPECL CLOCK OUTPUT
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Differential Output Voltage (VOD)
Duty Cycle
LVCMOS CLOCK OUTPUT
Output Frequency
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Output High Voltage (VOH)
Output Low Voltage (VOL)
Duty Cycle
Min Typ Max Unit
250
1.125
45
340
1.25
14
50
312.5
450
25
1.375
25
24
55
MHz
mV
mV
V
mV
mA
%
VS – 1.5
VS – 2.5
430
45
VS –1.05
VS –1.75
640
50
312.5
VS – 0.8
VS – 1.7
800
55
MHz
V
V
mV
%
VS − 0.1
45 50
62.5 MHz
V
0.1 V
55 %
Test Conditions/Comments
Termination = 100 Ω differential; default
Refer to Figure 2 for definition
Output shorted to GND
Refer to Figure 2 for definition
TIMING CHARACTERISTICS
Table 6.
Parameter
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
LVPECL
Output Rise Time, tRL
Output Fall Time, tFL
LVCMOS
Output Rise Time, tRC
Output Fall Time, tFC
Min Typ
150 200
150 200
180 250
180 250
0.50 0.70
0.50 0.70
Max Unit Test Conditions/Comments
Termination = 100 Ω differential; CLOAD = 0 pF
300 ps
20% to 80%, measured differentially
300 ps
80% to 20%, measured differentially
Termination = 200 Ω differential; CLOAD = 0 pF
300 ps
20% to 80%, measured differentially
300 ps
80% to 20%, measured differentially
Termination = 50 Ω to 0 V; CLOAD = 5 pF
1.10 ns
20% to 80%; CLOAD = 5 pF
1.10 ns
80% to 20%; CLOAD = 5 pF
Rev. 0 | Page 5 of 16
5 Page 
TERMINOLOGY
Phase Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount of
variation from ideal phase progression over time. This phenome-
non is called phase jitter. Although many causes can contribute
to phase jitter, one major cause is random noise, which is
characterized statistically as Gaussian (normal) in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in fre-
quency from the sine wave (carrier). The value is a ratio (expressed
in dB) of the power contained within a 1 Hz bandwidth with
respect to the power at the carrier frequency. For each measure-
ment, the offset from the carrier frequency is also given.
Phase Noise
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
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AD9575
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. In a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Because these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the Gaussian distribution.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable
to the device or subsystem being measured. The time jitter of
any external oscillators or clock sources has been subtracted.
This makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own time jitter to the total. In many cases, the
time jitter of the external oscillators and clock sources
dominates the system time jitter.
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD9575.PDF ] | |
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