MX25L12855E PDF даташит

Спецификация MX25L12855E изготовлена «Macronix International» и имеет функцию, называемую «128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY».

Детали детали

Номер произв	MX25L12855E
Описание	128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
Производители	Macronix International
логотип

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MX25L12855E

SECURED SERIAL FLASH SPECIFICATION

PRELIMINARY - PUBLIC

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P/N: PM1466

REV. 0.05, MAR. 05, 2009

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MX25L12855E

Contents

FEATURES................................................................................................................................................................... 5

GENERAL DESCRIPTION.......................................................................................................................................... 7

Table 1. Additional Features ..................................................................................................................................... 7

PIN CONFIGURATION................................................................................................................................................. 8

PIN DESCRIPTION....................................................................................................................................................... 8

BLOCK DIAGRAM....................................................................................................................................................... 9

DATA PROTECTION.................................................................................................................................................. 10

Table 2. Protected Area Sizes................................................................................................................................. 11

Table 3. 4K-bit Secured OTP Definition................................................................................................................... 11

Memory Organization............................................................................................................................................... 12

Table 4. Memory Organization............................................................................................................................... 12

DEVICE OPERATION................................................................................................................................................. 13

Figure 1-1. Serial Modes Supported (for Normal Serial mode)............................................................................... 13

Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)................................................. 13

COMMAND DESCRIPTION....................................................................................................................................... 14

Table 5. Command Sets.......................................................................................................................................... 14

(1) Write Enable (WREN)........................................................................................................................................ 16

(2) Write Disable (WRDI)......................................................................................................................................... 16

(3) Read Identification (RDID)................................................................................................................................. 16

(4) Read Status Register (RDSR)........................................................................................................................... 17

(5) Write Status Register (WRSR)........................................................................................................................... 18

Protection Modes.................................................................................................................................................... 18

(6) Read Data Bytes (READ).................................................................................................................................. 19

www.DataS(7h)eeRt4eUa.cdomData Bytes at Higher Speed (FAST_READ)............................................................................................ 19

(8) 2 x I/O Read Mode (2READ)............................................................................................................................. 19

(9) 4 x I/O Read Mode (4READ)............................................................................................................................. 20

(10) Fast Double Transfer Rate Read (FASTDTRD)............................................................................................... 20

(11) 2 x I/O Double Transfer Rate Read Mode (2DTRD)........................................................................................ 20

(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)........................................................................................ 21

(13) Sector Erase (SE)............................................................................................................................................ 21

(14) Block Erase (BE).............................................................................................................................................. 22

(15) Block Erase (BE32K)....................................................................................................................................... 22

(16) Chip Erase (CE)............................................................................................................................................... 22

(17) Page Program (PP).......................................................................................................................................... 23

(18) 4 x I/O Page Program (4PP)............................................................................................................................ 23

Program/Erase Flow(1) with read array data.......................................................................................................... 24

Program/Erase Flow(2) without read array data..................................................................................................... 25

(19) Continuously program mode (CP mode)......................................................................................................... 26

(20) Parallel Mode (Highly recommended for production throughputs increasing)................................................. 26

(21) Deep Power-down (DP)................................................................................................................................... 27

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MX25L12855E

(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES)................................................... 27

(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D).............................. 27

Table 6. ID Definitions ............................................................................................................................................ 28

(24) Enter Secured OTP (ENSO)............................................................................................................................ 28

(25) Exit Secured OTP (EXSO)............................................................................................................................... 28

(26) Read Security Register (RDSCUR)................................................................................................................. 28

Security Register Definition..................................................................................................................................... 29

(27) Write Security Register (WRSCUR)................................................................................................................. 29

(28) GPIO Expander................................................................................................................................................ 30

(28-1) GPIO Function Enable (GPIOEN)................................................................................................................ 30

(28-2) GPIO Function Disable (GPIODIS)............................................................................................................... 30

(28-3) GPIO Register Read/Write (GPIORW)......................................................................................................... 30

(28-4) GPIO Register Reset (GPIORST)................................................................................................................ 30

(29) Write Protection Selection (WPSEL)................................................................................................................ 32

WPSEL Flow........................................................................................................................................................... 32

(30) Single Block Lock/Unlock Protection (SBLK/SBULK)...................................................................................... 33

Block Lock Flow...................................................................................................................................................... 33

Block Unlock Flow................................................................................................................................................... 34

(31) Read Block Lock Status (RDBLOCK).............................................................................................................. 35

(32) Gang Block Lock/Unlock (GBLK/GBULK)........................................................................................................ 35

(33) Clear SR Fail Flags (CLSR)............................................................................................................................. 35

(34) Output Driving Configure (ODC)...................................................................................................................... 35

(35) Enable SO to Output RY/BY# (ESRY)............................................................................................................. 36

(36) Disable SO to Output RY/BY# (DSRY)............................................................................................................ 36

(37) Enter CFI Mode (ENCFI)................................................................................................................................. 36

www.DatPaSOhWeeEt4RU.-cOomN STATE.................................................................................................................................................... 37

ELECTRICAL SPECIFICATIONS.............................................................................................................................. 38

ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 38

Figure 2. Maximum Negative Overshoot Waveform................................................................................................ 38

CAPACITANCE TA = 25°C, f = 1.0 MHz.................................................................................................................. 38

Figure 3. Maximum Positive Overshoot Waveform................................................................................................. 38

Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL................................................................... 39

Figure 5. OUTPUT LOADING................................................................................................................................ 39

Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ........ 40

Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ....... 41

Timing Analysis......................................................................................................................................................... 43

Figure 6. Serial Input Timing................................................................................................................................... 43

Figure 7. Output Timing........................................................................................................................................... 43

Figure 8. Serial Input Timing for Double Transfer Rate Mode................................................................................. 44

Figure 9. Serial Output Timing for Double Transfer Rate Mode.............................................................................. 44

Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1...................................................... 45

Figure 11. Write Enable (WREN) Sequence (Command 06).................................................................................. 45

Figure 12. Write Disable (WRDI) Sequence (Command 04)................................................................................... 45

P/N: PM1466

REV. 0.05, MAR. 05, 2009

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Номер в каталоге	Описание	Производители
MX25L12855E	128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY	Macronix International
MX25L12855E	FLASH MEMORY	MACRONIX

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