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MX25L12845E PDF даташит
| Спецификация MX25L12845E изготовлена «Macronix International» и имеет функцию, называемую «128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY». |
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Детали детали
| Номер произв | MX25L12845E |
| Описание | 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY |
| Производители | Macronix International |
| логотип |  |
30 Pages
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MX25L12845E
MX25L12845E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
PRELIMINARY
www.DataSheet4U.com
P/N: PM1428
REV. 0.06, MAR. 05, 2009
1
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MX25L12845E
Contents
FEATURES................................................................................................................................................................... 5
GENERAL DESCRIPTION.......................................................................................................................................... 7
Table 1. Additional Features ..................................................................................................................................... 7
PIN CONFIGURATION................................................................................................................................................. 8
PIN DESCRIPTION....................................................................................................................................................... 8
BLOCK DIAGRAM....................................................................................................................................................... 9
DATA PROTECTION.................................................................................................................................................. 10
Table 2. Protected Area Sizes................................................................................................................................. 11
Table 3. 4K-bit Secured OTP Definition................................................................................................................... 11
Memory Organization............................................................................................................................................... 12
Table 4. Memory Organization............................................................................................................................... 12
DEVICE OPERATION................................................................................................................................................. 13
Figure 1-1. Serial Modes Supported (for Normal Serial mode)............................................................................... 13
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)................................................. 13
COMMAND DESCRIPTION....................................................................................................................................... 14
Table 7. Command Sets.......................................................................................................................................... 14
(1) Write Enable (WREN)........................................................................................................................................ 16
(2) Write Disable (WRDI)......................................................................................................................................... 16
(3) Read Identification (RDID)................................................................................................................................. 16
(4) Read Status Register (RDSR)........................................................................................................................... 17
(5) Write Status Register (WRSR)........................................................................................................................... 18
Protection Modes.................................................................................................................................................... 18
(6) Read Data Bytes (READ).................................................................................................................................. 19
(7) Read Data Bytes at Higher Speed (FAST_READ)............................................................................................ 19
(8) 2 x I/O Read Mode (2READ)............................................................................................................................. 19
(9) 4 x I/O Read Mode (4READ)............................................................................................................................. 20
www.DataSh(e1e0t4)UF.caosmt Double Transfer Rate Read (FASTDTRD)............................................................................................... 20
(11) 2 x I/O Double Transfer Rate Mode (2DTRD).................................................................................................. 20
(12) 4 x I/O Double Transfer Rate Mode (4DTRD).................................................................................................. 21
(13) Sector Erase (SE)............................................................................................................................................ 21
(14) Block Erase (BE).............................................................................................................................................. 22
(15) Block Erase (BE32K)....................................................................................................................................... 22
(16) Chip Erase (CE)............................................................................................................................................... 22
Program/Erase Flow(1) with read array data.......................................................................................................... 24
Program/Erase Flow(2) without read array data..................................................................................................... 25
(17) Page Program (PP).......................................................................................................................................... 26
(18) 4 x I/O Page Program (4PP)............................................................................................................................ 26
(19) Continuously program mode (CP mode)......................................................................................................... 26
(20) Parallel Mode (Highly recommended for production throughputs increasing)................................................. 27
(21) Deep Power-down (DP)................................................................................................................................... 27
(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES)................................................... 28
(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D).............................. 28
Table 8. ID Definitions ............................................................................................................................................ 29
(24) Enter Secured OTP (ENSO)............................................................................................................................ 29
(26) Read Security Register (RDSCUR)................................................................................................................. 29
(25) Exit Secured OTP (EXSO)............................................................................................................................... 30
Security Register Definition..................................................................................................................................... 30
(27) Write Security Register (WRSCUR)................................................................................................................. 30
P/N: PM1428
REV. 0.06, MAR. 05, 2009
2
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MX25L12845E
(28) Write Protection Selection (WPSEL)................................................................................................................ 31
WPSEL Flow........................................................................................................................................................... 31
(29) Single Block Lock/Unlock Protection (SBLK/SBULK)...................................................................................... 32
Block Lock Flow...................................................................................................................................................... 32
Block Unlock Flow................................................................................................................................................... 33
(30) Read Block Lock Status (RDBLOCK).............................................................................................................. 34
(31) Gang Block Lock/Unlock (GBLK/GBULK)........................................................................................................ 34
(32) Clear SR Fail Flags (CLSR)............................................................................................................................. 35
(33) Enable SO to Output RY/BY# (ESRY)............................................................................................................. 35
(34) Disable SO to Output RY/BY# (DSRY)............................................................................................................ 35
POWER-ON STATE.................................................................................................................................................... 36
ELECTRICAL SPECIFICATIONS.............................................................................................................................. 37
ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 37
Figure 2. Maximum Negative Overshoot Waveform................................................................................................ 37
CAPACITANCE TA = 25°C, f = 1.0 MHz.................................................................................................................. 37
Figure 3. Maximum Positive Overshoot Waveform................................................................................................. 37
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL................................................................... 38
Figure 5. OUTPUT LOADING................................................................................................................................ 38
Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ........ 39
Table 10. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ..... 40
Timing Analysis......................................................................................................................................................... 42
Figure 6. Serial Input Timing................................................................................................................................... 42
Figure 7. Output Timing........................................................................................................................................... 42
Figure 8. Serial Input Timing for Double Transfer Rate Mode................................................................................. 43
Figure 9. Serial Output Timing for Double Transfer Rate Mode.............................................................................. 43
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1...................................................... 44
Figure 11. Write Enable (WREN) Sequence (Command 06).................................................................................. 44
Figure 12. Write Disable (WRDI) Sequence (Command 04)................................................................................... 44
Figure 13. Read Identification (RDID) Sequence (Command 9F)........................................................................... 45
Figure 14. Read Identification (RDID) Sequence (Parallel)..................................................................................... 45
Figure 15. Read Status Register (RDSR) Sequence (Command 05)..................................................................... 46
www.DataSheFeti4gUu.rceom16. Write Status Register (WRSR) Sequence (Command 01).................................................................... 46
Figure 17. Read Data Bytes (READ) Sequence (Command 03)........................................................................... 47
Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B)........................................................ 47
Figure 19. Fast DT Read (FASTDTRD) Sequence (Command 0D)........................................................................ 48
Figure 20. 2 x I/O Read Mode Sequence (Command BB)...................................................................................... 48
Figure 21. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)................................................................ 49
Figure 22. 4 x I/O Read Mode Sequence (Command EB)...................................................................................... 49
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)............................................................... 50
Figure 24. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)................................................. 51
Figure 25. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED).......................... 52
Figure 26. Page Program (PP) Sequence (Command 02)..................................................................................... 53
Figure 27. 4 x I/O Page Program (4PP) Sequence (Command 38)....................................................................... 53
Figure 28. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)........................ 54
Figure 29. Sector Erase (SE) Sequence (Command 20)....................................................................................... 54
Figure 30. Block Erase (BE) Sequence (Command D8)........................................................................................ 54
Figure 31. Chip Erase (CE) Sequence (Command 60 or C7)................................................................................ 55
Figure 32. Deep Power-down (DP) Sequence (Command B9).............................................................................. 55
Figure 33. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)... 55
Figure 34. Release from Deep Power-down (RDP) Sequence (Command AB).................................................... 56
Figure 35. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)..... 56
Figure 36. READ ARRAY SEQUENCE (Parallel)................................................................................................... 57
Figure 37. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel).................................................................... 58
P/N: PM1428
REV. 0.06, MAR. 05, 2009
3
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| Номер в каталоге | Описание | Производители |
| MX25L12845E | 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY | Macronix International |
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