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QS532807 PDF даташит
| Спецификация QS532807 изготовлена «Integrated Device Technology» и имеет функцию, называемую «GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER». |
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Детали детали
| Номер произв | QS532807 |
| Описание | GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER |
| Производители | Integrated Device Technology |
| логотип |  |
6 Pages
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QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
QS532807
FEATURES:
− JEDEC compatible LVTTL level
− 10 low skew clock outputs
− Clock input is 5V tolerant
− Pinout and function compatible with QS5807
− 25Ω on-chip resistors available for low noise
− Input hysteresis for better noise margin
− Guaranteed low skew:
• 0.35ns output skew (same bank)
• 0.6ns output skew (different bank)
• 0.75ns part-to-part skew
− Available in QSOP and SOIC packages
DESCRIPTION:
The QS532807 clock driver/buffer circuit can be used for clock
buffering schemes where low skew is a key parameter. The QS532807
offers ten non-inverting outputs. Designed in IDT's proprietary QCMOS
process, these devices provide low propagation delay buffering with on-
chip skew of 0.35ns for same-transition, same bank signals. The
QS532807 has on-chip series termination resistors for lower noise clock
signals. The QS532807 series resistor version is recommended for
driving unterminated lines with capacitive loading and other noise
sensitive clock distribution circuits. These clock buffer products are
designed for use in high-performance workstations, embedded and
personal computing systems. Several devices can be used in parallel
or scattered throughout a system for guaranteed low skew, system-wide
clock distribution networks.
FUNCTIONAL BLOCK DIAGRAM
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IN
INDUSTRIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
1
O1
O2
O3
O4
O5
O6
O7
O8
O9
O 10
SEPTEMBER 2000
DSC - 5848
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QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
IN
GND
O1
VCC
O2
GND
O3
VCC
O4
GND
1 20
2 19
3 18
4 17
5 SO 20-2 16
6 SO 20-8 15
7 14
8 13
9 12
10 11
VCC
O 10
O9
GND
O8
VCC
O7
GND
O6
O5
QSOP/ SOIC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VTERM(2)
VTERM(3)
VAC
IOUT
Description
Max. Unit
Supply Voltage to Ground
– 0.5 to +4.6 V
DC Output Voltage VOUT
– 0.5 to VCC+0.5 V
DC Input Voltage VIN
– 0.5 to +7 V
AC Input Voltage (pulse width ≤20ns)
-3 V
DC Output Current VIN < 0
-20 mA
DC Output Current Max. Sink Current/Pin
120
mA
TSTG Storage Temperature
TJ Junction Temperature
– 65 to +150 °C
150 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE (TA = +25OC, f = 1.0MHz, VIN = 0V)
QSOP
SOIC
Pins Typ. Max. (1) Typ. Max. (1)
CIN 3 6 5 7
NOTE:
1. This parameter is guaranteed but not production tested.
Unit
pF
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PIN DESCRIPTION
Pin Names
IN
Ox
I/O Description
I Clock Input
O Clock Outputs
2
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QS532807
3.3V GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V
Symbol
VIH
VIL
VIC
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Clamp Diode Voltage (3)
Output HIGH Voltage
VOL Output LOW Voltage
IIN
IOFF
IOS
IODH
IODL
∆VT
ROUT
Input Leakage Current
Input Power Off Leakage
Short Circuit Current (2,3)
Output HIGH Current
Output LOW Current
Input Hysteresis
Output Resistance (4)
Test Conditions
Guaranteed Logic HIGH for All Inputs
Guaranteed Logic LOW for All Inputs
Vcc = Min., IIN = -18mA
Vcc = Min., IOH = -100µA
Vcc = Min., IOH = -8mA
Vcc = Min., IOL = 100µA
Vcc = Min., IOL = 6mA
Vcc = Min., IOL = 8mA
Vcc = Max., VIN = VCC or GND
Vcc = 0V, VIN = VCC or GND
Vcc = Max., VOUT = GND
Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V
Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V
VTLH - VTHL for All Inputs
Vcc = Min., IOL = 12mA
Min.
2
–0.5
—
Vcc - 0.2
2.4
—
—
—
—
—
–60
–50
50
—
—
Typ.(1)
1.7
—
–0.7
—
—
—
—
—
—
—
–195
–80
112
0.2
28
NOTES:
1. Typical values are at VCC = 3.3V, TA = 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
4. Output resistance represents the total output impedance of the logic device and includes added series termination resistance.
Max.
5.5
0.8
–1.2
—
—
0.2
0.4
0.5
±1
±1
—
–200
200
—
—
Unit
V
V
V
V
V
µA
µA
mA
mA
mA
V
Ω
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
www.DICaCtaSheet4QUu.iecsocment Power Supply Current
∆ICC Supply Current per Input HIGH
ICCD Dynamic Power Supply Current per Output (1)
IC Total Power Supply Current Examples (1,3)
Test Conditions
VCC = Max., VIN = GND or Vcc
VCC = Max., VIN = 3V
Input toggling at 50% duty cycle
VCC = Max., outputs Enabled
VCC = Max.,
Input at 50% duty cycle
fI = 10MHz
VCC = Max.,
Input at 50% duty cycle
fI = 2.5MHz
VIN = GND or Vcc
VIN = GND or Vcc
NOTES:
1. Guaranteed by design but not tested. CL = 0pF.
2. Typical values are for reference only. Conditions are VCC = 3.3V, TA = 25°C.
3. IC = ICC + (∆ICC)(DH)(NT) + ICCD (fO)(NO)
where:
DH = Input Duty Cycle
NT = Number of TTL HIGH inputs at DH (one)
fO = Output Frequency
NO = Number of outputs at fO (ten)
Typ. (2)
0.01
0.1
60
6
Max. Unit
100 µA
30 µA
90 µA/MHz
10 mA
1.5 3
3
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