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FDMF6730 PDF даташит
| Спецификация FDMF6730 изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Driver plus FET Multi-chip Module». |
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Детали детали
| Номер произв | FDMF6730 |
| Описание | Driver plus FET Multi-chip Module |
| Производители | Fairchild Semiconductor |
| логотип |  |
10 Pages
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August 2008
FDMF6730
Driver plus FET Multi-chip Module
Features
Over 95% efficiency
Internal 5V regulator for gate drive
6V-16V input range
1MHz max operating frequency
SMOD operation capability for light load efficiency
5A current capability (10A with PASS FET)
Current limit set by RDSON sensing to minimize power losses
Integrated bootstrap diode
Applications
Ultra Mobile PC
Notebook Computers
General Description
The FDMF6730 is a high efficiency Driver plus MOSFET power
stage solution optimized for Ultra Mobile PC (UMPC) system
power voltage supplies. It is fully compliant with the Intel Ultra-
Mobile Driver MOS (uDrMOS) Specification. The MOSFETs and
driver have been optimized to perform with high efficiency at
light and medium loads, ideal for compact PC devices.
The internal driver IC integrates two highly efficient LDOs for
internal gate-drive and external circuitry. The bootstrap diode is
also integrated within the IC. When operating with a single low
side MOSFET the uDrMOS module is capable of delivering up
to 5A of continuous current. The PASS transistor may be easily
routed in parallel with the low side MOSFET to provide up to
10A. The module also incorporates an over current protection
flag from an RDSON current sense architecture.
The device comes in a 6X6 Power QFN package for improved
thermal performance.
Typical Application
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LDO 5V OUT
LDO ENABLE
LDO OUT
PW M OUT
VCC
LDO 5V
VIN
BOOT
LDO EN
VSWH
LDO OUT
FDMF6730
LDO ADJ
PGND
LDRV
DRIVE HS
G_PASS
DRIVE LS
CS_OUT
D_PASS
CGND
CS_PROG S_PASS
VIN
VOUT
Figure 1. Power Train Application Circuit
Ordering Information
Part
FDMF6730
Current Rating
Max
[A]
10
Input Voltage
Typical
[V]
6-16
Frequency
Max
[KHz]
1000
©2008 Fairchild Semiconductor Corporation
FDMF6730 Rev. D2
1
Device
Marking
FDMF6730
www.fairchildsemi.com
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Functional Block Diagram
LDO_5V
LDO_EN
LDO_OUT
LDO_ADJ
DRIVE_HS
DRIVE_LS
5V Reg
LDO
Adjust
VCC
BOOT PHASE HDRV
OCP
C urren t
Trim m ing
V IN
VSW H
PGND
LDRV
G_PASS
D_PASS
Pin Configuration
CGND
CS_OUT
C S_P RO G
S_PASS
Figure 2. Functional Block Diagram
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PGND 40
PGND
PGND
LDRV
VSWH
D_PASS
G_PASS
S_PASS
S_PASS
S_PASS 31
1
A
(VSWH)
D
(D_PASS)
30
10
B
(VIN)
C
(CGND)
11 VIN
VIN
HDRV
VIN
CGND
PHASE
BOOT
LDO_5V
LDO_OUT
20 LDO_ADJ
21
Figure 3. 6mm X 6mm, 40L MLP Bottom View
2 www.fairchildsemi.com
FDMF6730 Rev. D2
No Preview Available ! |
Pin Description
Pin
1, 38 - 40
2 - 5, 36, A
6 - 12,14,B
13
15, 24, C
16
17
Name
PGND
VSWH
VIN
HDRV
CGND
PHASE
BOOT
18
19
20
21
22
23
25
26
27
28, 35, D
29
30-33
34
37
LDO_5V
LDO_OUT
LDO_ADJ
LDO_EN
DRIVE_LS
DRIVE_HS
VCC
CS_OUT
CS_PROG
D_PASS
NC
S_PASS
G_PASS
LDRV
Function
Low Side FET Source Pin. Connect to GND
Switch Node Pin. Low Side FET Drain pin. Electrically shorted to PHASE pin
Input Voltage Pin. Input voltage for buck converter
HDRV pin. High Side driver output. Connected to High Side FET gate pin.
IC Ground. Ground return for driver IC.
Switch Node Pin for easy bootstrap capacitor routing. Electrically shorted to VSWH pin.
Bootstrap Supply Input Pin. Provides voltage supply to high-side MOSFET driver. Connect
bootstrap capacitor.
5V Internal LDO Output.
Adjustable LDO Output.
LDO Adjust Input. Connect to external voltage divider to adjust LDO output.
Adjustable LDO Enable Pin. 1 = Enable, 0 = Disable
Low Side PWM Input. Connect to PWM controller.
High Side PWM Input. Connect to PWM controller.
Driver VCC. Connect to 5V.
Current Sense Output. 1 = Over-current Fault, 0 = No Fault.
Current Sense Program.
Pass FET Drain Pin. Connect to VSWH pad for higher output current.
No Connect. This pin must be floated. Must not be connected to any pin.
Pass FET Source Pin. Connect to PGND pad for higher output current.
Pass FET Gate Pin. Connect to LDRV pin for higher output current.
LDRV pin. Low Side driver output. Connect to G_PASS pin for higher output current.
Absolute Maximum Rating
Stresses exceeding the absolute maximum rating may damage the device. The device may not function or be operable above the
recommended operating conditions and stressing these parts to these levels is not recommended. In addition, extended exposure to
stresses above the recommended operating conditions may affect the device reliability. The absolute maximum rating are stress rat-
ings only.
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Min.
Max.
Units
VCC, Drive_LS, Drive_HS, LDO_EN, CS_Prog, CS_Out to GND
VIN to PGND
BOOT to VSWH
-0.3 6
-0.3 20
-0.3 6
V
V
V
VSWH to PGND
-1.0 27
V
BOOT to PGND
-0.3 27
V
IO(AV)
VIN = 8.4V, VO = 3.3V, fSW = 1MHz, TPCB = 130°C
IO(PK)
VIN = 8.4V, tPULSE = 10 s
RθJPCB
PT
Junction to PCB Thermal Resistance note 1.
TPCB =130°C
Operating and Storage Junction Temperature Range
-55
10 A
35 A
5.5 °C/W
3.3 W
150 °C
Note 1: Package power dissipation based on 4 layer, 2 square inch, 2 oz. copper pad. RθJPCB is the steady state junction to PCB
thermal resistance with PCB temperature referenced at VSWH pin.
3 www.fairchildsemi.com
FDMF6730 Rev. D2
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| Номер в каталоге | Описание | Производители |
| FDMF6730 | Driver plus FET Multi-chip Module | Fairchild Semiconductor |
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