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PDF AS8SLC512K32 Data sheet ( Hoja de datos )

Número de pieza AS8SLC512K32
Descripción 512K x 32 SRAM SRAM Memory Array MCM
Fabricantes Austin Semiconductor 
Logotipo Austin Semiconductor Logotipo



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No Preview Available ! AS8SLC512K32 Hoja de datos, Descripción, Manual

Austin Semiconductor, Inc.
SRAM
AS8SLC512K32
512K x 32 SRAM
SRAM Memory Array MCM
FEATURES
• Fast access times: 10, 12, 15, 17 and 20ns
• Fast OE\ access times: 6ns
• Ultra-low operating power < 1W worst case
• Single +3.3V ±0.3V power supply
• Fully static -- no clock or timing strobes necessary
• All inputs and outputs are TTL-compatible
• Easy memory expansion with CE\ and OE\ options
• Automatic CE\ power down
• High-performance, low-power consumption, CMOS
OPTIONS
Timing
10ns
12ns
15ns
17ns
20ns
MARKINGS
-10
-12
-15
-17
-20
• Package
Ceramic Quad Flatpack
Q No. 702
Ceramic Quad Flatpak(.054min SO) Q1
Pin Grid Array
P No.904
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q & Q1)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
2 627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 434 4
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
66 Lead PGA (P)
CS
\
CS
• Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
• 2V data retention/low power
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L
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8SLC512K32 is a 3.3V
16 Megabit CMOS SRAM Module organized as 512Kx32 bits. The
AS8SLC512K32 achieves very high speed access, low power
consumption and high reliability by employing advanced CMOS
memory technology.
This military temperature grade product is ideally suited for
commercial, industrial, and military applications when asynchronous high
speed switching and low ACTIVE opening power & ultra Fast Asyn-
chronous Access is mandated.
CS CS
M4
M3
M2
M1
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS8SLC512K32
Rev. 2.5 5/09
BLOCK DIAGRAM
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

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AS8SLC512K32 pdf
Austin Semiconductor, Inc.
SRAM
AS8SLC512K32
LOW POWER CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
CONDITIONS
All Inputs @ Vcc + 0.2V
or Vss + 0.2V,
CS\ = Vcc + 0.2V
VCC = 2V
VCC = 3V
SYMBOL
VDR
ICCDR
ICCDR
tCDR
MIN
2
0
Operation Recovery Time
tR 20
MAX
24
32
UNITS
V
mA
mA
ns
NOTES
4
ms 4, 11
LOW VCC DATA RETENTION WAVEFORM
VCC
CS\ 1-4
tCDR
111111111222222222333333333444444444555555555666666666777777777888888888999999999000000000111111111222222222333333333444444444555555555666666666777777777888888888
DATA RETENTION MODE
4.5V
VDR > 2V
4.5V
VDR
tR
111111111222222222333333333444444444555555555666666666777777777888888888999999999000000000111111111222222222333333333444441111111444411555552555522222222666663333333366663777774444444477774588888888855555555
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NOTES
1. All voltages referenced to V (GND).
SS
2. Worst case address switching.
3. ICC is dependent on output loading and cycle rates.
unloaded, and f=
1
t RC(MIN)
HZ.
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 & 2 unless otherwise noted.
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in
Fig. 2. Transition is measured +/- 200 mV typical from
steady state voltage, allowing for actual tester RC time
constant.
AS8SLC512K32
Rev. 2.5 5/09
7. At any given temperature and voltage condition,
t , is less than t , and t is less than t .
HZCS
LZCS
HZWE
LZWE
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and
output enable are held in their active state.
10. Address valid prior to or coincident with latest
occurring chip enable.
11. tRC= READ cycle time.
12. Chip enable (CS\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
13. ICC is for full 32 bit mode.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5

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AS8SLC512K32 arduino
www.DataSheet4U.com
Austin Semiconductor, Inc.
SRAM
AS8SLC512K32
ORDERING INFORMATION
EXAMPLE: AS8SLC512K32Q-17L/XT
Device Number
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
Package
Type
Q
Q
Q
Q
Q
Speed
ns
-10
-12
-15
-17
-20
Options Process
L /*
L /*
L /*
L /*
L /*
EXAMPLE: AS8SLC512K32P-12/IT
Device Number
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
Package
Type
P
P
P
P
P
Speed
ns
-10
-12
-15
-17
-20
Options Process
L /*
L /*
L /*
L /*
L /*
EXAMPLE: AS8SLC512K32Q1-12/XT
Device Number
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
Package
Type
Q1
Q1
Q1
Q1
Q1
Speed
ns
-10
-12
-15
-17
-20
Options Process
L /*
L /*
L /*
L /*
L /*
AS8SLC512K32
Rev. 2.5 5/09
*AVAILABLE PROCESSES
XT = Extended Temperature Rang
IT = Industrial Temperature Range
883C = Military Processing
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
OPTION DEFINITIONS
L = 2V data retention/low power
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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