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LF48410JC30 PDF даташит

Спецификация LF48410JC30 изготовлена ​​​​«LOGIC Devices Incorporated» и имеет функцию, называемую «1024 x 24-bit Video Histogrammer».

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Номер произв LF48410JC30
Описание 1024 x 24-bit Video Histogrammer
Производители LOGIC Devices Incorporated
логотип LOGIC Devices Incorporated логотип 

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LF48410JC30 Даташит, Описание, Даташиты
DEVICES INCORPORATED
DEVICES INCORPORATED
LF48410
1024 x 24-bit VideoLHFis4to8gr4am1m0er
1024 x 24-bit Video Histogrammer
FEATURES
DESCRIPTION
u 40 MHz Data Input and Compu-
tation Rate
u 1024 x 24-bit Memory Array
u Histograms of Images up to 4K x
4K with 10-bit Pixel Resolution
u Memory Array Flash Clear
u User-Programmable Modes:
Histogram, Histogram Accumulate,
Look Up Table, Bin Accumulate,
Delay Memory, Delay and Subtract,
Single Port RAM
u Replaces Harris HSP48410
u 84-pin PLCC, J-Lead
The LF48410 is capable of generating
histograms and Cumulative Distribu-
tion Functions of video images. It
may also be used as a look up table, a
bin accumulator, a delay memory
(delay and subtract also possible), or a
single port RAM. The on-chip 1024 x
24-bit memory array facilitates
histograms of images up to 4K x 4K
pixels with a 10-bit pixel resolution.
Once the histogram of a video image
is stored in the memory array, the
Cumulative Distribution Function can
be calculated by putting the device in
Histogram Accumulate Mode.
Transformation functions can be
performed on pixel values when the
device is in Look Up Table Mode. If
the Cumulative Distribution Function
is the desired transformation func-
tion, the LF48410 can calculate it and
have it available for Look Up Table
Mode. When the device is in Delay
Memory Mode, it functions as a video
row buffer. In this mode, the LF48410
can buffer video lines as long as 1029
pixels. The device can also function
as an asynchronous single port RAM.
During asynchronous modes, the
device can be configured as a 1024 x
24, 1024 x 16, or 1024 x 8-bit RAM. A
Flash Clear function is provided
which sets all memory array locations
and data path registers to “0”.
LF48410 BLOCK DIAGRAM
24
DIN23-0
IOA9-0
PIN9-0
10
10
CLK
(TO ALL REGISTERS)
WR
RD
UWS
START
FC
FCT2-0
LD
3
RAM ARRAY
DATA IN
DATA OUT
ADDRESS WR
ADDRESS
GENERATOR
COUNTER
ADDER
INPUT
CONTROL
CONTROL
FUNCTION
DECODE
MUX CONTROL SIGNALS
1
24
DIO DIO23-0
I/F
Video Imaging Products
08/08/2000–LDS.48410-L









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LF48410JC30 Даташит, Описание, Даташиты
DEVICES INCORPORATED
LF48410
1024 x 24-bit Video Histogrammer
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
When operating in a synchronous
mode, the rising edge of CLK strobes
all enabled registers. CLK has no
effect when operating in an asynchro-
nous mode.
Inputs
PIN9-0 — Pixel Data Input
PIN9-0 provides address information
to the memory array in Histogram,
Bin Accumulate, and Look Up Table
Modes. Data is latched on the rising
edge of CLK.
DIN23-0 — Data Input
In Bin Accumulate Mode, DIN23-0
provides data to the internal summer
to be added to data already in the
memory array. In Look Up Table
Mode, DIN23-0 is used to load the
memory array with the desired
values. In Delay Memory Mode, the
data to be delayed is input to the
memory array using DIN23-0, and in
Delay and Subtract Mode it also
provides data to be subtracted from
the delayed data. In all four modes,
DIN23-0 is latched on the rising edge
of CLK.
IOA9-0 — Asynchronous Address Input
IOA9-0 provides address information
to the memory array in Asynchronous
16 and 24 Modes.
FCT2-0 — Function Input
FCT2-0 is used to put the LF48410 into
one of its eight modes of operation
(Table 1). Data is latched on the
rising edge of LD. To ensure proper
operation of the device, START must
be HIGH while changing modes, and
there must be at least one rising edge
of CLK between the rising edge of LD
and the falling edge of START.
Inputs/Outputs
DIO23-0 — Data Input/Output
In all synchronous modes, DIO23-0 is
the 24-bit registered data output port.
In all asynchronous modes, DIO23-0 is
both the data input and data output
port for the memory array.
Controls
START — Device Enable
START is used to enable and disable
the synchronous modes of operation
(except for the Delay Memory and
Delay and Subtract Modes). The
synchronous mode sections explain
how START functions in each mode.
START has no effect in asynchronous
modes. Data is latched on the rising
edge of CLK. START must be held
HIGH when changing from one mode
to another. To ensure proper opera-
tion of the device, there must be at
least one rising edge of CLK between
the rising edge of LD and the falling
edge of START.
RD — Read/Output Enable
In all synchronous modes, RD is used
as an output enable for DIO23-0.
When RD is LOW, DIO23-0 is enabled
for output. When RD is HIGH, DIO23-0
is placed in a high-impedance state.
In all asynchronous modes, RD is
used as a read enable for the memory
array (see asynchronous mode
sections for details).
WR — Write Enable
In all asynchronous modes, WR is
used as a write enable for the
memory array (see asynchronous
mode sections for details). WR has
no effect in the synchronous modes.
UWS — Upper Word Select
UWS is only used in Asynchronous 16
Mode. If UWS is LOW and a memory
write is performed, data on DIO15-0 is
written to the lower 16 bits of the
addressed 24-bit word. If UWS is
LOW and a memory read is per-
formed, the lower 16 bits of the
addressed 24-bit word will be output
on DIO15-0. If UWS is HIGH and a
memory write is performed, data on
DIO7-0 is written to the upper 8 bits of
the addressed 24-bit word. If UWS is
HIGH and a memory read is per-
formed, the upper 8 bits of the
addressed 24-bit word will be output
on DIO7-0.
FC — Flash Clear
When FC is LOW, all memory array
locations and data path registers are
set to “0”. To ensure that Flash Clear
functions properly, FC should not be
set LOW until START is HIGH
(synchronous modes) or WR is HIGH
(asynchronous modes).
LD — Function Load Strobe
Data present on FCT2-0 is latched into
the LF48410 on the rising edge of LD.
To ensure proper operation of the
device, there must be at least one
rising edge of CLK between the rising
edge of LD and the falling edge of
START.
TABLE 1. LF48410 MODES
FCT2-0 MODE
0 0 0 Histogram
0 0 1 Histogram Accumulate
0 1 0 Delay and Subtract
0 1 1 Look Up Table
1 0 0 Bin Accumulate
1 0 1 Delay Memory
1 1 0 Asynchronous 24
1 1 1 Asynchronous 16
Video Imaging Products
2 08/08/2000–LDS.48410-L









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LF48410JC30 Даташит, Описание, Даташиты
DEVICES INCORPORATED
LF48410
1024 x 24-bit Video Histogrammer
HISTOGRAM MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
1. The memory array keeps track of
how many times a particular pixel
value is used in a video image. The
pixel value is input on PIN9-0 and is
latched on the rising edge of CLK.
Data at the address defined by PIN9-0
is read out of the memory array and
incremented by one. The data is then
written back to the memory array, in
the same location it was read from,
and is also output on DIO23-0 (if RD is
LOW). As long as START is LOW,
the device will be enabled for Histo-
gram Mode. When START is HIGH,
the device will still read pixel values,
but the addres-sed data will not be
incremented. The unchanged data is
output on DIO23-0 and is not written
back to the memory array (writing is
disabled). START is delayed inter-
nally three clock cycles to match the
latency of the address generator.
HISTOGRAM ACCUMULATE
MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
2. This mode is used to calculate the
Cumulative Distribution Function of
a video image. Before this can be
done, the histogram of the image
must already be in the memory array.
The internal counter is used to
generate address data for the memory
array. Data at the address defined by
the counter is read out of the memory
array and added to the sum of the
data from all previous address
locations. This new value is written
back to the memory array, in the
same location where the last read
occurred, and is also output on
DIO23-0 (if RD is LOW). After all
memory locations with histogram
data are accumulated, the memory
array will contain the Cumulative
Distribution Function.
After this mode is selected, the
internal counter and all data path
registers are reset to zero when
FIGURE 1. HISTOGRAM MODE
RAM ARRAY
DATA IN
DATA OUT
ADDRESS WR
PIN9-0
10
ADDRESS
GENERATOR
"0"
"1"
START
CONTROL
CLK TO ALL REGISTERS
FIGURE 2. HISTOGRAM ACCUMULATE MODE
24
DIO
I/F
DIO23-0
RD
CLK
(TO ALL REGISTERS)
START
RAM ARRAY
DATA IN
DATA OUT
ADDRESS WR
ADDRESS
GENERATOR
"0"
COUNTER
CONTROL
24
DIO
I/F
DIO23-0
RD
START is set LOW. Every rising edge
of CLK causes the counter to incre-
ment its output by one until the
counter reaches a value of 1023. At
this point, the counter will hold the
value of 1023 and writing to the
memory array will be disabled. As
long as START is LOW, the device
will be enabled for Histogram Accu-
mulate Mode. When START is HIGH,
the counter will still increment its
address values, but the addressed
data will not be added to anything.
The unchanged data is output on
DIO23-0 and is not written back to the
memory array (writing is disabled).
START is delayed internally three
clock cycles to match the latency of
the address generator.
LOOK UP TABLE MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
3. This mode is used to perform fixed
transformation functions on pixel
values. The transformation function
can be loaded into the memory array
in Look Up Table Write Mode,
Asynchronous 16/24 Mode, or
Histogram Accumulate Mode. In
Look Up Table Write Mode, data is
loaded into the memory array using
DIN23-0, CLK, and START. The
internal counter is used to generate
address data for the memory array.
When START goes LOW, the counter
is reset to zero. As long as START is
LOW, data on DIN23-0 is latched on
the rising edge of CLK and loaded
Video Imaging Products
3 08/08/2000–LDS.48410-L










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Номер в каталогеОписаниеПроизводители
LF48410JC301024 x 24-bit Video HistogrammerLOGIC Devices Incorporated
LOGIC Devices Incorporated

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