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LF2246QC25 PDF даташит

Спецификация LF2246QC25 изготовлена ​​​​«LOGIC Devices Incorporated» и имеет функцию, называемую «11 x 10-bit Image Filter».

Детали детали

Номер произв LF2246QC25
Описание 11 x 10-bit Image Filter
Производители LOGIC Devices Incorporated
логотип LOGIC Devices Incorporated логотип 

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LF2246QC25 Даташит, Описание, Даташиты
DEVICES INCORPORATED
DEVICES INCORPORATED
LF2246
11 x 10-bLit FIm2ag2e4Fi6lter
11 x 10-bit Image Filter
FEATURES
DESCRIPTION
u 66 MHz Data and Coefficient Input
and Computation Rate
u Four 11 x 10-bit Multipliers with
Individual Data and Coefficient
Inputs and a 25-bit Accumulator
u User-Selectable Fractional or
Integer Two’s Complement Data
Formats
u Fully Registered, Pipelined Archi-
tecture
u Input and Output Data Registers,
with User-Configurable Enables
u Three-State Outputs
u Fully TTL Compatible
u Ideally Suited for Image Processing
and Filtering Applications
u Replaces TRW/Raytheon/Fairchild
TMC2246
u 120-pin PQFPP
The LF2246 consists of an array of
four 11 x 10-bit registered multipliers
followed by a summer and a 25-bit
accumulator. All multiplier inputs
are user accessible and can be up-
dated every clock cycle with either
fractional or integer two’s comple-
ment data. The pipelined architecture
has fully registered input and output
ports and an asynchronous three-state
output enable control to simplify the
design of complex systems. The
pipeline latency for all inputs is five
clock cycles.
Storage for mixing and filtering
coefficients can be accomplished by
holding the data or coefficient inputs
over multiple clock cycles. A 25-bit
accumulator path allows cumulative
word growth which may be internally
rounded to 16 bits. Output data is
updated every clock cycle and may be
held under user control. All inputs,
outputs, and controls are registered
on the rising edge of clock, except for
OEN. The LF2246 operates at a clock
rate of 66 MHz over the full tempera-
ture and supply voltage ranges.
The LF2246 is applicable for perform-
ing pixel interpolation in image
manipulation and filtering applica-
tions. The LF2246 can perform a
bilinear interpolation of an image (4-
pixel kernels) at real-time video rates
when used with an image resampling
sequencer. Larger kernels or more
complex functions can be realized by
utilizing multiple devices.
Unrestricted access to all data and
coefficient input ports provides the
LF2246 with considerable flexibility in
applications such as digital filters,
adaptive FIR filters, mixers, and other
similar systems requiring high-speed
processing.
LF2246 BLOCK DIAGRAM
D19–0
ENSEL
C110–0
ENB1
D29–0
C210–0
ENB2
D39–0
C310–0 ENB3
D49–0
C410–0
ENB4
10 11 10 11
10 11 10 11
22
ACC
22
25
FSEL
OEN
CLK
MS LS
TO ALL REGISTERS
S15–0
2-11
OCEN
Video Imaging Products
08/16/2000–LDS.2246-K









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LF2246QC25 Даташит, Описание, Даташиты
DEVICES INCORPORATED
LF2246
11 x 10-bit Image Filter
FIGURE 1A. INPUT FORMATS
TABLE 1. INPUT REGISTER CONTROL
Data
Coefficient
Fractional Two’s Complement (FSEL = 0)
987
–20 2–1 2–2
(Sign)
210
2–7 2–8 2–9
10 9 8
–21 20 2–1
(Sign)
210
2–7 2–8 2–9
ENB1-4
1
1
0
ENSEL
1
0
X
INPUT REGISTER
HELD
Data ‘N
Coefficient ‘N
None
Integer Two’s Complement (FSEL = 1)
987
–29 28 27
(Sign)
210
22 21 20
10 9 8
–210 29 28
(Sign)
210
22 21 20
X = “Don’t Care”
N’ = 1, 2, 3, or 4
OCEN — Clock Enable
FIGURE 1B. OUTPUT FORMATS
Fractional Two’s Complement (FSEL = 0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9
(Sign)
Integer Two’s Complement (FSEL = 1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
(Sign)
When OCEN is LOW, data in the pre-
mux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register is
held preventing the output register’s
contents from changing (if FSEL does
not change). Accumulation continues
internally as long as ACC is HIGH,
despite the state of OCEN.
FSEL — Format Select
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.
Inputs
D19–0–D49–0 — Data Input
D1–D4 are 10-bit data input registers.
The LSB is DN0 (Figure 1a).
C110–0–C410–0 — Coefficient Input
C1–C4 are 11-bit coefficient input regis-
ters. The LSB is CN0 (Figure 1a).
Outputs
S15–0 — Data Output
The current 16-bit result is available on
the S15–0 outputs (Figure 1b).
Controls
ENB1–ENB4 — Input Enable
The ENBN (N = 1, 2, 3, or 4) input allows
either or both the DN and CN registers to
be updated on each clock cycle. When
ENBN is LOW, registers DN and CN are
both strobed by the next rising edge of
CLK. When ENBN is HIGH and ENSEL
is LOW, register DN is strobed while
register CN is held. If both ENBN and
ENSEL are HIGH, register DN is held,
and register CN is strobed (Table 1).
ENSEL — Enable Select
The ENSEL input in conjunction with
the individual input enables ENB1–
ENB4 determines whether the data or
the coefficient input registers will be
held on the next rising edge of CLK
(Table 1).
OEN — Output Enable
When the OEN signal is LOW, the cur-
rent data in the output register is avail-
able on the S15–0 pins. When OEN is
HIGH, the outputs are in a high-imped-
ance state.
When the FSEL input is LOW, the data
input during the current clock cycle is
assumed to be in fractional two’s
complement format, and the upper 16
bits of the accumulator are presented at
the output. Rounding of the accumula-
tor result to 16 bits is performed if the
accumulator control input ACC is
LOW. When FSEL is HIGH, the data
input is assumed to be in integer two’s
complement format, and the lower 16
bits of the accumulator are presented at
the output. No rounding is performed
when FSEL is HIGH.
ACC — Accumulator Control
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. If FSEL is also LOW,
one-half LSB rounding to 16 bits is per-
formed on the result. This allows sum-
mations without propagating roundoff
errors. When ACC is HIGH, the emerg-
ing product is added to the sum of the
previous products, without additional
rounding.
Video Imaging Products
2-12
08/16/2000–LDS.2246-K









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LF2246QC25 Даташит, Описание, Даташиты
DEVICES INCORPORATED
LF2246
11 x 10-bit Image Filter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to VCC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range (Ambient)
0°C to +70°C
–55°C to +125°C
Supply Voltage
4.75 V VCC 5.25 V
4.50 V VCC 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
VOH Output High Voltage
VCC = Min., IOH = –2.0 mA
VOL Output Low Voltage
VCC = Min., IOL = 4.0 mA
VIH Input High Voltage
VIL Input Low Voltage
(Note 3)
IIX Input Current
Ground VIN VCC (Note 12)
IOZ Output Leakage Current (Note 12)
ICC1 VCC Current, Dynamic
(Notes 5, 6)
ICC2 VCC Current, Quiescent (Note 7)
CIN Input Capacitance
TA = 25°C, f = 1 MHz
COUT Output Capacitance
TA = 25°C, f = 1 MHz
Min Typ Max Unit
2.4 V
0.4 V
2.0 VCC V
0.0 0.8 V
±10 µA
±40 µA
100 mA
6 mA
10 pF
10 pF
Video Imaging Products
2-13
08/16/2000–LDS.2246-K










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Номер в каталогеОписаниеПроизводители
LF2246QC2511 x 10-bit Image FilterLOGIC Devices Incorporated
LOGIC Devices Incorporated

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