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LF2242 PDF даташит

Спецификация LF2242 изготовлена ​​​​«LOGIC Devices Incorporated» и имеет функцию, называемую «12/16-bit Half-Band Interpolating/ Decimating Digital Filter».

Детали детали

Номер произв LF2242
Описание 12/16-bit Half-Band Interpolating/ Decimating Digital Filter
Производители LOGIC Devices Incorporated
логотип LOGIC Devices Incorporated логотип 

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LF2242 Даташит, Описание, Даташиты
DEVICES INCORPORATED
DEVICES INCORPORATED
LF2242
LF224212/16-bit Half-Band Interpolating/
12/16-bit Half-BaDnecdimInattinegrpDoigliatatilnFgilt/er
Decimating Digital Filter
FEATURES
DESCRIPTION
u 40 MHz Clock Rate
u Passband (0 to 0.22fS)
Ripple: ±0.02 dB
u Stopband (0.28fS to 0.5fS)
Rejection: 59.4 dB
u User-Selectable 2:1 Decimation or
1:2 Interpolation
u 12-bit Two’s Complement Input
and 16-bit Output with
User-Selectable Rounding, 8- to
16-Bits
u User-Selectable Two’s Complement
or Inverted Offset Binary Output
Formats
u Three-State Outputs
u Replaces TRW/ Raytheon/
Fairchild TMC2242
u Package Styles Available:
• 44-pin PLCC, J-Lead
• 44-pin PQFP
The LF2242 is a linear-phase, half-
band (low pass) interpolating/
decimating digital filter that, unlike
intricate analog filters, requires no
tuning. The LF2242 can also signifi-
cantly reduce the complexity of
traditional analog anti-aliasing pre-
filters without compromising the
signal bandwidth or attenuation. This
can be achieved by using the LF2242
as a decimating post-filter with an
A/D converter and by sampling the
signal at twice the rate needed.
Likewise, by using the LF2242 as an
interpolating pre-filter with a D/A
converter, the corresponding analog
reconstruction post-filter circuitry can
be simplified.
The coefficients of the LF2242 are
fixed, and the only user programming
required is the selection of the mode
(interpolate, decimate, or pass-
through) and rounding. The asyn-
chronous three-state output enable
control simplifies interfacing to a bus.
Data can be input into the LF2242 at a
rate of up to 40 million samples per
second. Within the 40 MHz I/O limit,
the output sample rate can be one-
half, equal to, or two times the input
sample rate. Once data is clocked in,
the 55-value output response begins
after 7 clock cycles and ends after 61
clock cycles. The pipeline latency
from the input of an impulse response
to its corresponding output peak is 34
clock cycles.
The output data may be in either
two’s complement format or inverted
offset binary format. To avoid
truncation errors, the output data is
always internally rounded before it is
latched into the output register.
Rounding is user-selectable, and the
output data can be rounded from 16
bit values down to 8 bit values.
DC gain of the LF2242 is 1.0015
(0.0126 dB) in pass-through and
decimate modes and 0.5007 (–3.004
dB) in interpolate mode. Passband
ripple does not exceed ±0.02 dB from
0 to 0.22fS with stopband attenuation
greater than 59.4 dB from 0.28fS to
0.5fS (Nyquist frequency). The
response of the filter is –6 dB at 0.25fS.
Full compliance with CCIR Recom-
mendation 601 (–12 dB at 0.25fS) can
be achieved by cascading two devices
serially.
LF2242 BLOCK DIAGRAM
TCO RND2–0
3
12
SI11–0
INTERPOLATION 12
CIRCUIT
3
55-TAP
FIR
FILTER
3
ROUND
AND LIMIT
CIRCUIT
16
DECIMATION
CIRCUIT
3
16
SO15–0
CLK TO ALL REGISTERS
INT DEC SYNC
1
OE
Video Imaging Products
08/16/2000–LDS.2242-K









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LF2242 Даташит, Описание, Даташиты
DEVICES INCORPORATED
LF2242
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
FIGURE 1. FREQUENCY RESPONSE OF FILTER
0
–10
–20
–30
Controls
INT — Interpolation Control
When INT is LOW and DEC is HIGH
(Table 1), the device internally forces
every other incoming data sample to
zero. This effectively halves the input
data rate and the output amplitude.
–40
–50
–60
–70
–80
0
0.1ƒS
0.2ƒS
0.3ƒS
0.4ƒS
0.5ƒS
DEC — Decimation Control
When DEC is LOW and INT is HIGH
(Table 1), the output register is strobed on
every other rising edge of CLK (driven at
half the clock rate), decimating the output
data stream.
FREQUENCY (NORMALIZED)
TABLE 1. MODE SELECTION
INT DEC
MODE
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Inputs
SI11–0 — Data Input
12-bit two’s complement data input
port. Data is latched into the register on
the rising edge of CLK. The LSB is SI0
(Figure 2).
0 0 Pass-through*
0 1 Interpolate
1 0 Decimate
1 1 Pass-through*
*Input and output registers run at full
clock rate
Clock
Outputs
CLK — Master Clock
SO15-0 Data Output
The rising edge of CLK strobes all regis-
ters. All timing specifications are refer-
enced to the rising edge of CLK.
SYNC — Synchronization Control
Incoming data is synchronized by hold-
ing SYNC HIGH on CLKN, and then by
bringing SYNC LOW on CLKN+1 with
the first word of input data. SYNC is held
LOW until resynchronization is desired,
or it can be toggled at half the clock rate.
For interpolation (INT = LOW), input
data should be presented at the first ris-
ing edge of CLK for which SYNC is LOW
and then at every alternate rising edge of
CLK thereafter. SYNC is inactive if DEC
and INT are equal (pass-through mode).
The current 16-bit result is available on
the SO15-0 outputs. The LF2242’s limiter
ensures that a valid full-scale (7FFF
positive or 8000 negative) output will be
generated in the event of an internal
overflow. The LSB is SO0 (Figure 2).
Video Imaging Products
2 08/16/2000–LDS.2242-K









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LF2242 Даташит, Описание, Даташиты
DEVICES INCORPORATED
LF2242
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
FIGURE 2. INPUT AND OUTPUT FORMATS
Two’s Complement Input Format
11 10 9 8
–20 2–1 2–2 2–3
(Sign)
3210
2–8 2–9 2–10 2–11
Two’s Complement Output Format (TCO = 1, Non-interpolate)
15 14 13 12
–20 2–1 2–2 2–3
(Sign)
3210
2–12 2–13 2–14 2–15
Two’s Complement Output Format (TCO = 1, Interpolate)
15 14 13 12
–21 20 2–1 2–2
(Sign)
3210
2–11 2–12 2–13 2–14
Inverted Offset Binary Output Format (TCO = 0, Non-interpolate)
15 14 13 12
20 2–1 2–2 2–3
(Sign)
3210
2–12 2–13 2–14 2–15
Inverted Offset Binary Output Format (TCO = 0, Interpolate)
15 14 13 12
21 20 2–1 2–2
(Sign)
3210
2–11 2–12 2–13 2–14
RND2-0 — Rounding Control
The rounding control inputs set the posi-
tionoftheeffectiveLSBoftheoutputdata
by adding a rounding bit to the internal
bit position that is one below that speci-
fied by RND2-0. All bits below the effec-
tive LSB position are subsequently ze-
roed (Table 2).
TCO — Two’s Complement Format
Control
The TCO input determines the format of
the output data. When TCO is HIGH, the
output data is presented in two’s comple-
ment format. When TCO is LOW, the
data is in inverted offset binary format
(all output bits are inverted except the
MSB — the MSB is unchanged).
OE — Output Enable
When the OE signal is LOW, the current
data in the output register is available on
the SO15-0 pins. When OE is HIGH, the
outputs are in a high-impedance state.
TABLE 2. ROUNDING FORMAT
RND2-0 SO15 SO14 SO13 SO12 • • •
SO8 SO7 SO6 SO5 SO4 SO3 SO2 SO1 SO0
000 X X X X • • • X X X X X X X X R
001 X X X X • • • X X X X X X X R 0
010 X X X X • • • X X X X X X R 0 0
011 X X X X • • • X X X X X R 0 0 0
100 X X X X • • • X X X X R 0 0 0 0
101 X X X X • • • X X X R 0 0 0 0 0
110 X X X X • • • X X R 0 0 0 0 0 0
111 X X X X • • • X R 0 0 0 0 0 0 0
'R' indicates the half-LSB rounded bit (effective LSB position)
Video Imaging Products
3 08/16/2000–LDS.2242-K










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