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PDF LF13007 Data sheet ( Hoja de datos )
| Número de pieza | LF13007 | |
| Descripción | Digital Gain Set | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 1995
LF13006 LF13007 Digital Gain Set
General Description
The LF13006 and LF13007 are precision digital gain sets
used for accurately setting non-inverting op amp gains
Gains are set with a 3-bit digital word which can be latched
in with WR and CS pins All digital inputs are TTL and CMOS
compatible
The LF13006 shown below will set binary scaled gains of 1
2 4 8 16 32 64 and 128 The LF13007 will set gains of 1
2 5 10 20 50 and 100 (a common attenuator sequence)
In addition both versions have several taps and two uncom-
mitted matching resistors that allow customization of the
gain
The gains are set with precision thin film resistors The low
temperature coefficient of the thin film resistors and their
excellent tracking result in gain ratios which are virtually in-
dependent of temperature
The LF13006 LF13007 used in conjunction with an amplifi-
er not only satisfies the need for a digitally programmable
amplifier in microprocessor based systems but is also use-
ful for discrete applications eliminating the need to find
0 5% resistors in the ratio of 100 to 1 which track each
other over temperature
Features
Y TTL and CMOS compatible logic levels
Y Microprocessor compatible
Y Gain error 0 5% max
Y Binary or scope knob gains
Y Wide supply range a 5V to g 18V
Y Packaged in 16-pin DIP
Block Diagram and Typical Application (LF13006)
Note Rj 15 kX
Order Number LF13006N or LF13007N
See NS Package Number N16A
TL H 5114 – 1
C1995 National Semiconductor Corporation TL H 5114
RRD-B30M115 Printed in U S A
1 page  
Application Information
FLOW-THROUGH OPERATION
THE LF13006 LF13007 can be operated with control lines
CS and WR grounded In this mode new data on the digital
inputs will immediately set the new gain value Input data
cannot be latched in this mode
INPUT CURRENT
Current flowing through the input (pin 2) due to bias current
of the op amp will result in a gain error due to switch imped-
ance Normally this error is very small For example 10 nA
of bias current flowing through 3 kX of switch resistance will
result in an error of 30 mV at the summing node However
applications that have significant current flowing through the
input must take this effect into account
SETTLING TIME
Settling time is a function of the particular op amp used with
the LF13006 7 and the gain that is selected It can be opti-
mized and stability problems can be prevented through the
use of a lead capacitor from the inverting input to the output
of the amplifier A lead capacitor is effective whenever the
feedback around an amplifier is resistive whether with dis-
crete resistors or with the LF13006 7 It compensates for
the feedback pole created by the parallel resistance and
capacitance from the inverting input of the op amp to AC
ground
Settling Time Test Circuit
TL H 5114 – 6
Typical Settling Time Curves
Unstable at CL less than 2 pF
Typical Applications
Variable Capacitance Multiplier
Ceffective e C1(gain set )
Note Output swing at input op amp
is multiplied by set gain Signal
range may be limited
TL H 5114 – 7
Variable Time Constant Filter
R
Time constant e C1
N
N e setting of LF13006
1
(range e to 1)
128
TL H 5114 – 8
5
TL H 5114 – 9
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LF13007.PDF ] | |
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