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PDF LTC2241-10 Data sheet ( Hoja de datos )
| Número de pieza | LTC2241-10 | |
| Descripción | 210Msps ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2241-10
10-Bit, 210Msps ADC
FEATURES
wwwn.daStaashmeeptl4eu.cRoamte: 210Msps
n 60.5dB SNR
n 78dB SFDR
n 1.2GHz Full Power Bandwidth S/H
n Single 2.5V Supply
n Low Power Dissipation: 585mW
n LVDS, CMOS, or Demultiplexed CMOS Outputs
n Selectable Input Ranges: ±0.5V or ±1V
n No Missing Codes
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Data Ready Output Clock
n Pin Compatible Family
250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)
210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)
170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)
185Msps: LTC2220-1 (12-Bit)*
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)*
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*
n 64-Pin 9mm × 9mm QFN Package
APPLICATIONS
n Wireless and Wired Broadband Communication
n Cable Head-End Systems
n Power Amplifier Linearization
n Communications Test Equipment
DESCRIPTION
The LTC®2241-10 is a 210Msps, sampling 10-bit A/D con-
verter designed for digitizing high frequency, wide dynamic
range signals. The LTC2241-10 is perfect for demanding
communications applications with AC performance that
includes 60.5dB SNR and 78dB SFDR. Ultralow jitter of
95fsRMS allows IF undersampling with excellent noise
performance.
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data
rate or two demultiplexed buses running at half data rate
with either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 2.625V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance over a wide range of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.
TYPICAL APPLICATION
REFH
REFL
ANALOG
INPUT
FLEXIBLE
REFERENCE
+
INPUT
S/H
–
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
2.5V
VDD
10-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
0.5V
TO 2.625V
OVDD
D9
• CMOS
• OR
• LVDS
D0
OGND
224110 TA01
SFDR vs Input Frequency
85
80
75
70
65
60
1V RANGE
55
50
2V RANGE
45
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224110 G11
224110fb
1
1 page  
LTC2241-10
POWER REQUIREMENTS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VDD Analog Supply Voltage
wwwP.dSaLEtaEPsheet4u.cSolmeep Mode Power
PNAP Nap Mode Power
LVDS OUTPUT MODE
(Note 8)
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
● 2.375
2.5
1
28
2.625
V
mW
mW
OVDD
IVDD
Output Supply Voltage
Analog Supply Current
(Note 8)
● 2.375
●
2.5
226
2.625
252
V
mA
IOVDD
PDISS
Output Supply Current
Power Dissipation
●
58 70
mA
●
710 805
mW
CMOS OUTPUT MODE
OVDD
IVDD
Output Supply Voltage
Analog Supply Current
(Note 8)
(Note 7)
● 0.5
●
2.5 2.625
226 252
V
mA
PDISS
Power Dissipation
585 mW
TIMING CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fS Sampling Frequency
tL ENC Low Time (Note 7)
(Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●1
210
● 2.26 2.38 500
● 1.5 2.38 500
MHz
ns
ns
tH ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
● 2.26 2.38 500
● 1.5 2.38 500
ns
ns
tAP Sample-and-Hold Aperture Delay
0.4 ns
tOE Output Enable Delay
LVDS OUTPUT MODE
tD ENC to DATA Delay
tC ENC to CLKOUT Delay
DATA to CLKOUT Skew
Rise Time
Fall Time
Pipeline Latency
CMOS OUTPUT MODE
tD ENC to DATA Delay
tC ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline
Latency
Full Rate CMOS
Demuxed Interleaved
Demuxed Simultaneous
(Note 7)
(Note 7)
(Note 7)
(tC – tD) (Note 7)
(Note 7)
(Note 7)
(tC – tD) (Note 7)
● 5 10
●1
●1
● –0.6
1.7
1.7
0
0.5
0.5
5
2.8
2.8
0.6
●1
●1
● –0.6
1.7
1.7
0
5
2.8
2.8
0.6
5
5 and 6
ns
ns
ns
ns
ns
ns
Cycles
ns
ns
ns
Cycles
Cycles
Cycles
224110fb
5
5 Page 
FUNCTIONAL BLOCK DIAGRAM
LTC2241-10
www.datashAeINe+ t4u.com
INPUT
AIN– S/H
VCM
2.2μF
1.25V
REFERENCE
RANGE
SELECT
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
VDD
GND
SHIFT REGISTER
AND CORRECTION
SENSE
REF
BUF
REFH
REFL INTERNAL CLOCK SIGNALS
DIFFERENTIAL
DIFF
REF
AMP
INPUT
LOW JITTER
CLOCK
CONTROL
LOGIC
DRIVER
REFLB REFHA
2.2μF
0.1μF
1μF
REFLA REFHB
0.1μF ENC+
1μF
ENC–
M0DE LVDS SHDN OE
OUTPUT
DRIVERS
OVDD
+
+–
–
OF
D9
•
•
•
+
–+
–
D0
CLKOUT
OGND
224110 F01
Figure 1. Functional Block Diagram
224110fb
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2241-10.PDF ] | |
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