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LM1881N PDF даташит

Спецификация LM1881N изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «LM1881 Video Sync Separator».

Детали детали

Номер произв LM1881N
Описание LM1881 Video Sync Separator
Производители National Semiconductor
логотип National Semiconductor логотип 

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LM1881N Даташит, Описание, Даташиты
February 1995
LM1881 Video Sync Separator
General Description
The LM1881 Video sync separator extracts timing informa-
tion including composite and vertical sync burst back porch
timing and odd even field information from standard nega-
tive going sync NTSC PAL and SECAM video signals with
amplitude from 0 5V to 2V p-p The integrated circuit is also
capable of providing sync separation for non-standard fast-
er horizontal rate video signals The vertical output is pro-
duced on the rising edge of the first serration in the vertical
sync period A default vertical output is produced after a
time delay if the rising edge mentioned above does not oc-
cur within the externally set delay period such as might be
the case for a non-standard video signal
Features
Y AC coupled composite input signal
Y l10 kX input resistance
Y k10 mA power supply drain current
Y Composite sync and vertical outputs
Y Odd even field output
Y Burst gate back porch output
Y Horizontal scan rates to 150 kHz
Y Edge triggered vertical output
Y Default triggered vertical output for non-standard video
signal (video games-home computers)
Connection Diagram
LM1881N
Order Number LM1881M or LM1881N
See NS Package Number M08A or N08E
TL H 9150 – 1
PAL in this datasheet refers to European broadcast TV standard ‘‘Phase Alternating Line’’ and not to Programmable Array Logic
C1995 National Semiconductor Corporation TL H 9150
RRD-B30M115 Printed in U S A









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LM1881N Даташит, Описание, Даташиты
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
13 2V
Input Voltage
Output Sink Currents Pins 1 3 5
3 Vpp (VCC e 5V)
6 Vpp (VCC t 8V)
5 mA
Output Sink Current Pin 7
2 mA
Package Dissipation (Note 1)
1100 mW
Operating Temperature Range
0 C b 70 C
Storage Temperature Range
b65 C to a150 C
ESD Susceptibility (Note 2)
2 kV
Soldering Information
Dual-In-Line Package (10 sec )
Small Outline Package
Vapor Phase (60 sec )
Infrared (15 sec )
260 C
215 C
220 C
See AN-450 ‘‘Surface Mounting Methods and their Effect on
Product Reliability’’ for other methods of soldering surface
mount devices
Electrical Characteristics
VCC e 5V Rset e 680 kX TA e 25 C Unless otherwise specified
Parameter
Conditions
Typ Tested
Design
Units
Limit (Note 3) Limit (Note 4) (Limits)
Supply Current
DC Input Voltage
Outputs at Logic 1
Pin 2
VCC e 5V
VCC e 12V
52
55
15
10
12
13
18
mAmax
mAmax
Vmin
Vmax
Input Threshold Voltage
Note 5
70 55
85
mVmin
mVmax
Input Discharge Current
Pin 2 VIN e 2V
11 6
16
mAmin
mAmax
Input Clamp Charge Current
RSET Pin Reference Voltage
Pin 2 VIN e 1V
Pin 6 Note 6
08 02
1 10
1 22 1 35
mAmin
Vmin
Vmax
Composite Sync Vertical
Outputs
Burst Gate Odd Even
Outputs
Composite Sync Output
Vertical Sync Output
Burst Gate Output
Odd Even Output
Vertical Sync Width
IOUT e 40 mA
Logic 1
VCC e 5V
VCC e 12V
IOUT e 1 6 mA
Logic 1
VCC e 5V
VCC e 12V
IOUT e 40 mA
Logic 1
VCC e 5V
VCC e 12V
IOUT e b1 6 mA Logic 0 Pin 1
IOUT e b1 6 mA Logic 0 Pin 3
IOUT e b1 6 mA Logic 0 Pin 5
IOUT e b1 6 mA Logic 0 Pin 7
45
36
45
02
02
02
02
230
40
11 0
24
10 0
40
11 0
08
08
08
08
190
300
Vmin
Vmin
Vmin
Vmin
Vmin
Vmin
Vmax
Vmax
Vmax
Vmax
msmin
msmax
Burst Gate Width
2 7 kX from Pin 5 to VCC
25
4 47
msmin
msmax
Vertical Default Time
Note 7
65 32
90
msmin
msmax
Note 1 For operation in ambient temperatures above 25 C the device must be derated based on a 150 C maximum junction temperature and a package thermal
resistance of 110 C W junction to ambient
Note 2 ESD susceptibility test uses the ‘‘human body model 100 pF discharged through a 1 5 kX resistor’’
Note 3 Typicals are at TJ e 25 C and represent the most likely parametric norm
Note 4 Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 5 Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse
Note 6 Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1 3 5 and 7) to the RSET pin (Pin 6)
Note 7 Delay time between the start of vertical sync (at input) and the vertical output pulse
2









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LM1881N Даташит, Описание, Даташиты
Typical Performance Characteristics
Rset Value Selection
vs Vertical Serration
Pulse Separation
Vertical Default
Sync Delay Time
vs Rset
Burst Black Level
Gate Time vs Rset
Vertical Pulse
Width vs Rset
Vertical Pulse
Width vs Temperature
Supply Current vs
Supply Voltage
TL H 9150 – 2
3










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