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PDF LM1290N Data sheet ( Hoja de datos )
| Número de pieza | LM1290N | |
| Descripción | Autosync Horizontal Deflection Processor | |
| Fabricantes | National Semiconductor | |
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January 1997
LM1290
Autosync Horizontal Deflection Processor
General Description
The LM1290 is a high-performance, low-cost deflection solu-
tion for autosync monitors.
The LM1290 provides full autosync capability, DC controls
and complete freedom from manufacturing trims. Its continu-
ous capture range is from 22 kHz to 110 kHz (1:5). Mode
change frequency ramping, for protection of the horizontal
deflection output transistor, is programmable by using an ex-
ternal capacitor.
Together with the National Semiconductor LM1296 Raster
Geometry Correction System for Multi-Frequency Displays,
excellent performance is offered. The two-chip solution pro-
vides the advantage of good jitter performance, simplified
board layout, and lower system cost.
The LM1290 is packaged in a 14-pin plastic DIP package.
Features
n Full autosync — 22 kHz to 110 kHz with no component
switching or external adjustments
n No manufacturing trims needed — internal VCO
capacitor trimmed on chip
n Sample-and-hold circuit for fast top-of-screen phase
recovery, even when using composite sync
n DC-controlled H phase and duty cycle
n Resistor-programmable minimum VCO frequency
n Excellent jitter performance
n X-ray input disables H drive until VCC powered down
n Low VCC disables H drive (VCC < 8.5V)
n H output transistor protected against accidental turn on
during flyback
n Capacitor-programmable frequency ramping, dfVCO / dt,
protects H output transistor during scanning mode
changes
Connection Diagram
FIGURE 1.
Order Number LM1290N
See NS Package Number N14A
DS012917-1
© 1999 National Semiconductor Corporation DS012917
www.national.com
1 page  
Pin Descriptions
See Figure 4 through Figure 10 for input and output sche-
matics.
Pin 1 — fMIN: A resistor from this pin to ground sets the free
run frequency of the LM1290. The free run frequency should
be set typically as:
fMIN = 0.85(fMINLOCK) − 2 kHz
where fMINLOCK is the minimum lock frequency required for
the application. The resistance required to set this frequency
is approximately:
For example, to find RMIN for VGA which has fMINLOCK =
31.469 kHz,
fMIN = 0.85(31.469 kHz) − 2 kHz = 24749
Rounding to the closest standard 1% resistor gives RMIN =
21.5 kΩ.
Pin 2 — H/HV POLARITY: A 0.1 µF capacitor is connected
from this pin to ground for detecting the polarity of H/HV sync
at pin 3. A low logic level at pin 2 indicates active-high H/HV
sync to pin 3, a high level indicates active-low. See Figure 4
for the output schematic.
Pin 3 — H/HV SYNC: This input pin accepts DC-coupled H
or composite sync of either polarity. For best noise immunity,
a resistor of 2 kΩ or less should be connected from this pin
to pin 8 (GND) via a short path. See Figure 5 for the input
schematic.
Pin 4 — DUTY CYCLE: A DC voltage applied to this pin sets
the duty cycle of the H DRIVE output (pin 7), with a range of
approximately 30% to 70%. 2V sets the duty cycle to ap-
proximately 50%. See Figure 6 for the input schematic.
Pin 5 — X-RAY: This pin is for monitoring CRT anode volt-
age. If the input voltage exceeds an internal threshold, H
Input/Output Schematics
DRIVE output (pin 7) is latched high. VCC has to be reduced
to below approximately 2V to clear the latched condition, i.e.,
power must be turned off. See Figure 7 for the input sche-
matic.
Pin 6 — FLYBACK: Input pin for phase detector 2. For best
operation, the flyback peak should be at least 5V but not
greater than VCC. Any pulse width greater than 1.5 µs is ac-
ceptable. See Figure 8 for the input schematic.
Pin 7 — H DRIVE: This is an open-collector output which
provides the drive pulse for the high power deflection circuit.
The pulse duty cycle is controlled by pin 4. Polarity conven-
tion: Horizontal deflection output transistor is on when H
DRIVE OUT is low. See Figure 9 for the output schematic.
Pin 8 — GND: System ground. For best jitter performance,
all bypass capacitors should be connected to this pin via
short paths.
Pin 9 — PD2 FILTER: The low-pass filter cap of between
0.01 µF to 1 µF for the output of phase detector 2 is con-
nected from this pin to pin 8 (GND) via a short path. A
smaller value increases the response.
Pin 10 — PHASE: A DC control voltage applied to this pin
sets the phase of the flyback pulse with respect to the center
of H sync. See Figure 10 for the input schematic.
Pin 11 — FVC FILTER: A 1 µF capacitor is connected from
this pin to pin 8 (GND) via a short path.
Pin 12 — PD1 OUT/VCO IN: Phase detector 1 has a gated
charge pump output which requires an external low-pass fil-
ter. For best jitter performance, the filter should be grounded
to pin 8 (GND) via a short path. If a voltage source is applied
to this pin, the phase detector is disabled and the VCO can
be controlled directly.
Pin 13 — VREF: This is the decoupling pin for the internal
8.2V reference. It should be decoupled to pin 8 (GND) via a
short path with a cap of at least 470 µF. Do not load this pin.
Pin 14 — VCC: 12V nominal power supply pin. This pin
should be decoupled to pin 8 (GND) via a short path with a
cap of at least 47 µF.
FIGURE 4.
DS012917-4
5
DS012917-5
FIGURE 5.
www.national.com
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