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PDF LPC2917 Data sheet ( Hoja de datos )
| Número de pieza | LPC2917 | |
| Descripción | (LPC2917 / LPC2919) ARM9 microcontroller | |
| Fabricantes | NXP Semiconductors | |
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LPC2917/19
ARM9 microcontroller with CAN and LIN
Rev. 1.01 — 15 November 2007
Preliminary data sheet
1. Introduction
1.1 About this document
This document lists detailed information about the LPC2917/19 device. It focuses on
factual information like pinning, characteristics etc. Short descriptions are used to outline
the concept of the features and functions. More details and background on developing
applications for this device are given in the LPC2917/19 User Manual (see Ref. 1). No
explicit references are made to the User Manual.
1.2 Intended audience
This document is written for engineers evaluating and/or developing systems, hard-
and/or software for the LPC2917/19. Some basic knowledge of ARM processors and
architecture and ARM968E-S in particular is assumed (see Ref. 2).
2. General description
2.1 Architectural overview
The LPC2917/19 consists of:
• An ARM968E-S processor with real-time emulation support
• An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
• Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem)
• Three VLSI Peripheral Buses (VPB - a compatible superset of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems.
The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All
peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB2VPB bridge used in the subsystems contains a write-ahead buffer
one transaction deep. This implies that when the ARM968E-S issues a buffered write
action to a register located on the VPB side of the bridge, it continues even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.
1 page  
NXP Semiconductors
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5. Block diagram
LPC2917/19
ARM9 microcontroller with CAN and LIN
LPC2917/19
ITCM
16 Kb
ARM968E-S
DTCM
16 Kb
Vectored Interrupt
Controller (VIC)
sm
s
Embedded
FLASH Memory
512/768 Kb
FLASH Memory Controller (FMC)
Modulation and Sampling
Control Subsystem
Timer 0, 1 (MTMR)
PWM 0, 1, 2, 3
ADC 1, 2
s
s
s
s
s
s
CAN Controller
0, 1
GLOBAL ACCEPTANCE
FILTER
2 Kbyte Static RAM
LIN MASTER 0/1
s
s
IEEE 1149.1 JTAG TEST and
DEBUG INTERFACE
External Static Memory
Controller (SMC)
Embedded
SRAM Memory 16 Kb
SRAM Controller #1
Embedded
SRAM Memory 32 Kb
SRAM Controller #0
General Subsystem
Chip Feature ID (CFID)
System Control Unit (SCU)
Event Router (ER)
Peripheral Subsystem
General Purpose IO (GPIO)
0, 1, 2, 3
Timer (TMR)
0, 1, 2, 3
SPI 0, 1, 2
UART 0, 1
Watchdog Timer (WDT)
Power Clock Reset
Control Subsystem
Clock Generation Unit (CGU)
s
Reset Generation Unit (RGU)
Power Management Unit (PMU)
Multi-layer AHB
system bus
m = master port
s = slave port
Fig 1. LPC2917/19 block diagram
LPC2917_19_1
Preliminary data sheet
Rev. 1.01 — 15 November 2007
© NXP B.V. 2007. All rights reserved.
5 of 68
5 Page 
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
www.DataSheet4U.com
7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also
referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test
pins can be used to connect a debugger probe for the embedded ARM processor. Pin
JTAGSEL selects between boundary-scan mode and debug mode. Table 5 shows the
boundary- scan test pins.
Table 5. IEEE 1149.1 boundary-scan test and debug interface
Symbol
Description
JTAGSEL
TAP controller select input. LOW level selects ARM debug mode and HIGH level
selects boundary scan and flash programming; pulled up internally
TRSTN
test reset input; pulled up internally (active LOW)
TMS
test-mode select input; pulled up internally
TDI test data input, pulled up internally
TDO
test data output
TCK
test clock input
7.1.4 Power supply pins description
Table 6 shows the power supply pins.
Table 6. Power supplies
Symbol
Description
VDD(CORE)
VSS(CORE)
VDD(IO)
VSS(IO)
VDD(OSC)
VSS(OSC)
VDD(A3V3)
VSS(PLL)
digital core supply 1.8 V
digital core ground (digital core, ADC 1)
I/O pins supply 3.3 V
I/O pins ground
oscillator and PLL supply
oscillator ground
ADC 3.3 V supply
PLL ground
7.2 Clocking strategy
7.2.1 Clock architecture
The LPC2917/19 contains several different internal clock areas. Peripherals like Timers,
SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All
base clocks are generated by the Clock Generator Unit (CGU). They may be unrelated in
frequency and phase and can have different clock sources within the CGU.
The system clock for the CPU and AHB Multilayer Bus infrastructure has its own base
clock. This means most peripherals are clocked independently from the system clock. See
Figure 3 for an overview of the clock areas within the device.
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of the Power
Management Unit (PMU) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase. See Section 8.8 for
more details of clock and power control within the device.
LPC2917_19_1
Preliminary data sheet
Rev. 1.01 — 15 November 2007
© NXP B.V. 2007. All rights reserved.
11 of 68
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