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PDF C8051F021 Data sheet ( Hoja de datos )

Número de pieza C8051F021
Descripción (C8051F020 - C8051F023) 8K ISP FLASH MCU Family
Fabricantes Silicon Laboratories　
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C8051F020/1/2/3
8K ISP FLASH MCU Family
ANALOG PERIPHERALS
- SAR ADC
• 12-Bit (C8051F020/1)
• 10-Bit (C8051F022/3)
• ± 1 LSB INL
• Programmable Throughput up to 100 ksps
• Up to 8 External Inputs; Programmable as Single-Ended or
Differential
• Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
• Data-Dependent Windowed Interrupt Generator
• Built-in Temperature Sensor (± 3°C)
- 8-bit ADC
www.DataSheet4U.com • Programmable Throughput up to 500 ksps
• 8 External Inputs
• Programmable Amplifier Gain: 4, 2, 1, 0.5
- Two 12-bit DACs
• Can Synchronize Outputs to Timers for Jitter-Free Wave-
form Generation
- Two Analog Comparators
- Voltage Reference
- Precision VDD Monitor/Brown-Out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
- On-Chip Debug Circuitry Facilitates Full- Speed, Non-
Intrusive In-Circuit/In-System Debugging
- Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor; Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
- IEEE1149.1 Compliant Boundary Scan
- Low-Cost, Complete Development Kit
HIGH SPEED 8051 µC CORE
- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
- Up to 25 MIPS Throughput with 25 MHz Clock
- 22 Vectored Interrupt Sources
MEMORY
- 4352 Bytes Internal Data RAM (4k + 256)
- 64k Bytes FLASH; In-System programmable in 512-byte
Sectors
- External 64k Byte Data Memory Interface (programma-
ble multiplexed or non-multiplexed modes)
DIGITAL PERIPHERALS
- 8 Byte-Wide Port I/O (C8051F020/2); 5V tolerant
- 4 Byte-Wide Port I/O (C8051F021/3); 5V tolerant
- Hardware SMBus™ (I2C™ Compatible), SPI™, and
Two UART Serial Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with
5 Capture/Compare Modules
- 5 General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer; Bi-directional Reset Pin
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16 MHz
- External Oscillator: Crystal, RC, C, or Clock
- Real-Time Clock Mode using Timer 3 or PCA
SUPPLY VOLTAGE .......................... 2.7V TO 3.6V
- Typical Operating Current: 10 mA @ 20 MHz
- Multiple Power Saving Sleep and Shutdown Modes
100-Pin TQFP and 64-Pin TQFP Packages Available
Temperature Range: -40°C to +85°C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
VREF
10/12-bit
100ksps
ADC
12-Bit
DAC
12-Bit
DAC
8-bit
PGA 500ksps
ADC
++
--
VOLTAGE
COMPARATORS
DIGITAL I/O
UART0
UART1
SMBus
SPI Bus
Port 0
Port 1
Port 2
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Port 3
Port 4
Port 5
Port 6
Port 7
64 pin 100 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
22
INTERRUPTS
64KB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
JTAG
CLOCK
SANITY
CIRCUIT CONTROL
Preliminary Rev. 1.4 12/03
Copyright © 2003 by Silicon Laboratories
C8051F020/1/2/3-DS14
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1 page




C8051F021 pdf
C8051F020/1/2/3
16.1. Accessing XRAM..........................................................................................................145
16.1.1. 16-Bit MOVX Example.......................................................................................145
16.1.2. 8-Bit MOVX Example.........................................................................................145
16.2. Configuring the External Memory Interface .................................................................146
16.3. Port Selection and Configuration ..................................................................................146
16.4. Multiplexed and Non-multiplexed Selection.................................................................148
16.4.1. Multiplexed Configuration ..................................................................................148
16.4.2. Non-multiplexed Configuration...........................................................................149
16.5. Memory Mode Selection ...............................................................................................150
16.5.1. Internal XRAM Only ...........................................................................................150
www.DataSheet4U.com 16.5.2. Split Mode without Bank Select ..........................................................................150
16.5.3. Split Mode with Bank Select ...............................................................................151
16.5.4. External Only .......................................................................................................151
16.6. Timing .......................................................................................................................151
16.6.1. Non-multiplexed Mode........................................................................................153
16.6.1.1. 16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’................................153
16.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’............154
16.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ..............................155
16.6.2. Multiplexed Mode................................................................................................156
16.6.2.1. 16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’................................156
16.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’............157
16.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ..............................158
17. PORT INPUT/OUTPUT .....................................................................................................161
17.1. Ports 0 through 3 and the Priority Crossbar Decoder....................................................163
17.1.1. Crossbar Pin Assignment and Allocation ............................................................163
17.1.2. Configuring the Output Modes of the Port Pins ..................................................164
17.1.3. Configuring Port Pins as Digital Inputs ...............................................................165
17.1.4. External Interrupts (IE6 and IE7) ........................................................................165
17.1.5. Weak Pull-ups......................................................................................................165
17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])......................................165
17.1.7. External Memory Interface Pin Assignments ......................................................166
17.1.8. Crossbar Pin Assignment Example......................................................................168
17.2. Ports 4 through 7 (C8051F020/2 only)..........................................................................177
17.2.1. Configuring Ports which are not Pinned Out.......................................................177
17.2.2. Configuring the Output Modes of the Port Pins ..................................................177
17.2.3. Configuring Port Pins as Digital Inputs ...............................................................178
17.2.4. Weak Pull-ups......................................................................................................178
17.2.5. External Memory Interface ..................................................................................178
18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................183
18.1. Supporting Documents ..................................................................................................184
18.2. SMBus Protocol.............................................................................................................185
18.2.1. Arbitration............................................................................................................185
18.2.2. Clock Low Extension...........................................................................................185
18.2.3. SCL Low Timeout ...............................................................................................186
18.2.4. SCL High (SMBus Free) Timeout.......................................................................186
Rev. 1.4
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C8051F021 arduino
C8051F020/1/2/3
Figure 9.1. Voltage Reference Functional Block Diagram....................................................91
Figure 9.2. REF0CN: Reference Control Register ................................................................92
Table 9.1. Voltage Reference Electrical Characteristics ......................................................92
10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93
Figure 10.1. Voltage Reference Functional Block Diagram ...................................................93
Figure 10.2. REF0CN: Reference Control Register ................................................................94
Table 10.1. Voltage Reference Electrical Characteristics ......................................................94
11. COMPARATORS..................................................................................................................95
Figure 11.1. Comparator Functional Block Diagram ..............................................................95
Figure 11.2. Comparator Hysteresis Plot.................................................................................96
www.DataSheet4U.com Figure 11.3. CPT0CN: Comparator0 Control Register ...........................................................97
Figure 11.4. CPT1CN: Comparator1 Control Register ...........................................................98
Table 11.1. Comparator Electrical Characteristics.................................................................99
12. CIP-51 MICROCONTROLLER........................................................................................101
Figure 12.1. CIP-51 Block Diagram ......................................................................................101
Table 12.1. CIP-51 Instruction Set Summary.......................................................................103
Figure 12.2. Memory Map .....................................................................................................107
Table 12.2. Special Function Register (SFR) Memory Map................................................109
Table 12.3. Special Function Registers ................................................................................109
Figure 12.3. SP: Stack Pointer ...............................................................................................113
Figure 12.4. DPL: Data Pointer Low Byte ............................................................................113
Figure 12.5. DPH: Data Pointer High Byte ...........................................................................113
Figure 12.6. PSW: Program Status Word ..............................................................................114
Figure 12.7. ACC: Accumulator............................................................................................115
Figure 12.8. B: B Register .....................................................................................................115
Table 12.4. Interrupt Summary.............................................................................................117
Figure 12.9. IE: Interrupt Enable ...........................................................................................119
Figure 12.10. IP: Interrupt Priority ........................................................................................120
Figure 12.11. EIE1: Extended Interrupt Enable 1 .................................................................121
Figure 12.12. EIE2: Extended Interrupt Enable 2 .................................................................122
Figure 12.13. EIP1: Extended Interrupt Priority 1.................................................................123
Figure 12.14. EIP2: Extended Interrupt Priority 2.................................................................124
Figure 12.15. PCON: Power Control.....................................................................................126
13. RESET SOURCES ..............................................................................................................127
Figure 13.1. Reset Sources ....................................................................................................127
Figure 13.2. Reset Timing .....................................................................................................128
Figure 13.3. WDTCN: Watchdog Timer Control Register ...................................................131
Figure 13.4. RSTSRC: Reset Source Register.......................................................................132
Table 13.1. Reset Electrical Characteristics .........................................................................133
14. OSCILLATORS...................................................................................................................135
Figure 14.1. Oscillator Diagram ............................................................................................135
Figure 14.2. OSCICN: Internal Oscillator Control Register .................................................136
Table 14.1. Internal Oscillator Electrical Characteristics.....................................................136
Figure 14.3. OSCXCN: External Oscillator Control Register...............................................137
15. FLASH MEMORY ..............................................................................................................139
Rev. 1.4
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