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PDF 8272 Data sheet ( Hoja de datos )
| Número de pieza | 8272 | |
| Descripción | Single / Double Density Floppy Disk Controller | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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8272
SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLER
&amstrad;
IBM Compatible in Both Single and Double Density Recording Formats
Programmable Data Record Lengths: 128,256,512, or 1024 Bytes/Sector
www.DataSheetM4Uu.clotmi-Sector and Multi-Track Transfer Capability
Drive up to 4 Floppy Disks
Data Scan Capability - Will Scan a Single Sector or an Entire Cylinder's Worth of Data
Fields, Comparing on a Byte by Byte Basis, Data in the Processor's Memory with Data
Read from the Diskette
Data Transfers in DMA or Non-DMA Mode
Parallel Seek Operations on Up to Four Drives
Compatible with Most Microprocessors including 8080A,8085A,8086 and 8088
Single-Phase 8 Mhz Clock
Single +5 Volt Power Supply
Available in 40-Pin Plastic Dual-in-Line Package
The 8272 is a LSI Floppy Disk Controller (FDC) Chip, which contains the curcuitry and control
functions for interfacing a processor to 4 Floppy Disk Drives. It is capable of supporting either
IBM 3740 single density format (FM), or IBM System 34 Double Density format (MFM) including
double sided recording. The 8272 provides control signals which simplify the design of an
external phase locked loop, and write precompensation circuitry. The FDC simplifies and
handles most of the burdens associated with implementing a Floppy Disk Drive Interface.
PIN CONFIGURATION
1 page  
NO.
1 RST
TO
I
µP
2 /RD
I¹
µP
3 /WR
I¹
µP
4
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/CS
I
5 A0
I¹
6-13 DB0-DB7 I/O ¹
14 DRQ
O
µP
µP
µP
DMA
15 /DACK I
DMA
16 TC
I
17 IDX
18 INT
19 CLK
20 GND
40 Vcc
39
/RW /
SEEK
I
O
I
O
DMA
FDD
µP
FDD
38 LCT/DIR O
FDD
Reset: Places FDC in idle
state. Resets output lines to
FDD to "0" (low)
Read: Control signal for
transfer of data from FDC to
Data Bus, when "0" (low).
Write: Control signal for
transfer of data to FDC via
Data Bus, when "0" (low).
Chip Select: IC selected
when "0" (low),
allowing /RD and /WR
enabled.
Data/Status Reg Select:
Selects Data Reg (A0=1), or
Status Reg (A0=0) content
be send to Data Bus.
Data Bus: Bidirectional 8-bit
Data Bus
Data DMA Request: DMA
Request is being made by
FDC when DRQ "1"
DMA Acknowledge: DMA
cycle is active when
"0" (low) and Controller is
performing DMA transfer.
Terminal Count: Indicates
the termination of a DMA
transfer when "1" (high)
Index: Indicates the
beginning of a disk track
Interrupt: Interrupt request
generated by FDC
Clock: Single Phase 8 Mhz
Squarewave Clock
Ground: D.C. Power Return
D.C. POWER +5v
Read Write/SEEK: When
"1" (high) Seek mode
selected and when "0"
Read/Write mode selected.
Low Current/Direction:
Lowers write current on
inner tracks in Read/Write
mode, determines direction
head will step in seek mode.
Fault Reset/Step: Resets
fault FF in FDD in
Read/Write mode, provides
5 Page 
W
W
W
Command
W
W
W
Execution
R
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R
R
Result R
R
R
R
H
R
N
EOT
GPL
DTL
ST0
ST1
ST2
C
H
R
N
Sector ID Information prior
to command execution
Data transfer between the
FDD and main system
FDC reads all of cylinders
contents from index hole
to EOT
Status information after
command execution
Sector ID information after
command execution
Phase R/W
W
Command
W
Execution
Result
R
R
R
R
R
R
R
D7 D6
0 MFM
00
READ ID
Data Bus
D5 D4 D3 D2
0 01 0
0 0 0 HDS
ST0
ST1
ST2
C
H
R
N
D1
1
DS1
D0
0
DS0
Remarks
Command Codes
The first correct ID
information on the cylinder
is stored in Data Register
Status information after
command execution
Sector ID information
during Execution Phase
Phase R/W
W
W
Command W
W
D7 D6
0 MFM
00
FORMAT A TRACK
Data Bus
D5 D4 D3 D2 D1
0 01 1
0
0 0 0 HDS DS1
N
SC
D0
1
DS0
Remarks
Command Codes
Bytes/sector
Sectors/Cylinder
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet 8272.PDF ] | |
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