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C6845 PDF даташит

Спецификация C6845 изготовлена ​​​​«Cast» и имеет функцию, называемую «CRT Controller Megafunction».

Детали детали

Номер произв C6845
Описание CRT Controller Megafunction
Производители Cast
логотип Cast логотип 

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C6845 Даташит, Описание, Даташиты
C6845
CRT Controller
Megafunction
General Description
The C6845 Cathode Ray Tube Controller (CRTC) interfaces a microprocessor to a raster-scan CRT display.
The C6845 is a synchronous, synthesizable VHDL megafunction, functionally equivalent to the Motorola
www.DataSheet4U.McoCm6845 CRT Controller.
The microprocessor access 19 registers (1 Address and 18 Data Registers) within the C6845 in order to
provide video timing, refresh memory addresses, cursor, and light pen strobe signals. CRT video timing signals
include Vertical Sync (VS), Horizontal Sync (HS), and Display Enable (DE) output signals. Refresh memory
addressing includes Memory Address (MA[13:0]) and Row Address (RA[4:0]) output buses.
The C6845 microprocessor interface consist of unidirectional data input (DIN[7:0]) and data output
(DOUT[7:0]) buses and control signals RS, RWn, CSn, and E. Optionally, an available bus wrapper converts
the unidirectional data buses into an 8-bit bi-directional data bus (D[7:0]). This is the pin equivalent to the
MC6845.
Features
Fully-synchronous, synthesizable VHDL Megafunction, functionally equivalent to Motorola MC6845
Capable of driving alphanumeric, semi-graphic, or bit-mapped graphics displays
Wide range of programmable alphanumeric screen formats
Programmable registers controlling output signals Vertical Sync (VS), Horizontal Sync (HS), and
Display Enable (DE) signals
Programmable horizontal line rate and sync pulse width
Programmable vertical frame rate
Programmable registers controlling Memory Address (MA[13:0]) start address
Programmable Start Address Register for Hardware Scrolling
Programmable registers controlling Row Address (RA[4:0]) size, yielding a character row
Programmable register controlling Normal Sync (Non-Interlace), Interlace Sync, or Interlace Sync &
Video Mode
Programmable registers for control and format of Cursor
Light Pen Register
Microprocessor 8-bit Data Bus and Control Interface
CAST, Inc.
March 2004
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C6845 Даташит, Описание, Даташиты
CAST C6845 Megafunction Datasheet
Symbol
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Microprocessor
Interface
PDBTRI
DOUT[7..0]
DIN[7..0]
RS
RWn
CSn
E
Light Pen Strobe
LPSTB
Reset & Clock
RESETn
CLK
PU_RESETn
C6845
CRT
Controller
VS
HS
DE
MA[13..0]
RA[4..0]
CURSOR
CRT
Control
Refresh Memory/
Charactor Generator
Addressing
Cursor
Pin Description
Name
DIN[7..0]
DOUT[7..0]
PDBTRI
RS
RWn
CSn
E
LPSTB
RESETn
CLK
PU_RESETn
DE
HS
VS
MA[13..0]
RA[4..0]
CURSOR
Applications
Type
Polarity
Description
Microprocessor Interface
IN -
Data Bus Input
OUT -
Data Bus Output
Processor Data Bus Tri-state
OUT
(See Description)
Control
H= Processor Reads
L= Processor Writes
IN Low Address Register Select
High
Data Register Select
IN Low Write to Internal Register
High
Read Internal Register
IN Low Chip Select
IN
High
Enable Data Bus Output During
Microprocessor Reads
Falling Edge
Register Data During
Microprocessor Writes
Light Pen Strobe Interface
IN
Rising Edge
Light Pen Strobe
Reset and Clock Interface
IN Low Reset/Test Mode
IN
Falling Edge
Synchronous Clock (Except for
Micro-processor Interface)
IN Low Asynchronous Power-up Reset
CRT Control Interface
OUT High
Display Enable
OUT High
Horizontal Sync
OUT High
Vertical Sync
Refresh Memory/Character Generator Addressing Interface
OUT -
Refresh Memory Address
OUT -
Row Address
Cursor Interface
OUT High
Cursor
Point-of-contact Kiosk
CAST, Inc.
Page 2









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C6845 Даташит, Описание, Даташиты
CAST C6845 Megafunction Datasheet
Medical instrumentation
Test & Measurement Instrumentation
Industrial Equipment
Avionics
Gaming & Amusement Machines
Block Diagram
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CLK
RESETN
DE
HS
Horizontal
Counter
Set Reset
Register
Horizontal
Sync Width
Counter
CLK Character
RESETN
Row
Counter
Set Reset
Register
Vertical
VS Control
PU_RESETn
CO
CO
CO
CO
CO
CO
CO
CO
Cursor
Scan
Line
Counter
Linear
Address
Generator
CO
Cursor
Control
Light Pen Sync
CO
RA(4:0)
MA(13:0)
LPSTB CLK
Address Register
And Decoder
R0
Horizontal
Total Reg
R1
Horizontal
Displayed Reg
R2
Sync Position
Reg
R3 Horizontal Sync
Width Reg
R4
Vertical
Total Reg
R5 Vertical Total
Adjust Reg
R6
Vertical
Displayed Reg
R7 Vertical Sync
Position Reg
R8 Interlace Mode
Reg
R9 Max Scan Line
Address Reg
R10 Cursor Start
Reg
R11 Cursor End
Reg
R12 Start Address
R13 Reg
R14 Cursor Address
R15 Reg
R16
R17
Light
Pen
Reg
RWN
CSN
RS
E
PDBTRI
DIN[7:0]
DOUT[7:0]
Functional Description
This section describes the Block Diagram above. A description of each of the blocks in the diagram is given
here.
CAST, Inc.
Page 3










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