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PDF MTP7N20E Data sheet ( Hoja de datos )
| Número de pieza | MTP7N20E | |
| Descripción | TMOS POWER FET | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Designer's
™ Data Sheet
TMOS E-FET .™
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
www.DataSheet4cUri.tciocmal and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
G
®
D
S
Order this document
by MTP7N20E/D
MTP7N20E
Motorola Preferred Device
TMOS POWER FET
7.0 AMPERES
200 VOLTS
RDS(on) = 0.70 OHMS
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
VDSS
VDGR
VGS
VGSM
200 Vdc
200 Vdc
± 20 Vdc
± 40 Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TC = 25°C
Derate above 25°C
ID 7.0 Adc
ID 3.8
IDM 21 Apk
PD 50 Watts
0.4 W/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Adc, L = 10 mH, RG = 25 Ω)
TJ, Tstg
EAS
– 55 to 150
74
°C
mJ
Thermal Resistance — Junction to Case°
— Junction to Ambient°
RθJC
RθJA
2.5°
62.5°
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1
1 page  
12
10
8
Q1
6
180
QT
150
VGS
120
Q2
90
4 60
TJ = 25°C
2 ID = 7 A 30
Q3 VDS
00
0 2 4 6 8 10 12 14
QG, TOTAL GATE CHARGE (nC)
www.DataSheet4U.comFigure
8.
Gate–To–Source and
Voltage versus Total
Drain–To–Source
Charge
1000 TJ = 25°C
ID = 7 A
VDS = 100 V
VGS = 10 V
100
tr
td(off)
10 td(on)
MTP7N20E
tf
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
7
VGS = 0 V
6 TJ = 25°C
5
4
3
2
1
0
0.5 0.6 0.7 0.8 0.9 1.0 1.1
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–Gener-
al Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MTP7N20E.PDF ] | |
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