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79RC32438 PDF даташит

Спецификация 79RC32438 изготовлена ​​​​«Integrated Device Technology» и имеет функцию, называемую «IDTTM InterpriseTM Integrated Communications Processor».

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Номер произв 79RC32438
Описание IDTTM InterpriseTM Integrated Communications Processor
Производители Integrated Device Technology
логотип Integrated Device Technology логотип 

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79RC32438 Даташит, Описание, Даташиты
IDTTM InterpriseTM Integrated
Communications Processor
79RC32438
Features
32-bit CPU Core
– MIPS32 instruction set
– Cache Sizes: 16KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
– 16 dual-entry JTLB with variable page sizes
– 3-entry instruction TLB
www.DataSheet4U.c3o-mentry data TLB
– Max issue rate of one 32x16 multiply per clock
– Max issue rate of one 32x32 multiply every other clock
– CPU control with start, stop and single stepping
– Software breakpoints support
– Hardware breakpoints on virtual addresses
– Enhanced JTAG and ICE Interface that is compatible with v2.5
of the EJTAG Specification
DDR Memory Controller
– Supports up to 2GB of DDR SDRAM
– 2 chip selects (each chip select supports 4 internal DDR
banks)
– Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit
devices
– Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR
SDRAM devices
– Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
– Automatic refresh generation
Memory and Peripheral Device Controller
– Provides “glueless” interface to standard SRAM, Flash, ROM,
dual-port memory, and peripheral devices
– Demultiplexed address and data buses: 16-bit data bus, 26-bit
address bus, 6 chip selects, supports alternate bus masters,
control for external data bus buffers
– Supports 8-bit and 16-bit width devices
Automatic byte gathering and scattering
– Flexible protocol configuration parameters: programmable
number of wait states (0 to 63), programmable postread/post-
write delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
– Write protect capability per chip select
– Programmable bus transaction timer generates warm reset
when counter expires
– Supports up to 64 MB of memory per chip select
Counter/Timers
– Three general purpose 32-bit counter timers
PCI Interface
– 32-bit PCI revision 2.2 compliant (3.3V only)
– Supports host or satellite operation in both master and target
modes
– Support for synchronous and asynchronous operation
– PCI clock supports frequencies from 16 MHz to 66 MHz
– PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
– I2O “like” PCI Messaging Unit
Block Diagram
MII MII
MIPS-32
CPU Core
Interrupt
Controller
:
:
2 Ethernet
ICE
EJTAG
MMU
D. Cache I. Cache
3 Counter
Timers
10/100
Interfaces
DDR &
DDR
Device
Controllers
IPBusTM
On-Chip
Memory
DMA
Controller
Arbiter
I2C
Controller
2 UARTS
(16550)
GPIO
Interface
SPI
Controller
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory & I2C Bus
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins SPI Bus
PCI Bus
© 2004 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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79RC32438 Даташит, Описание, Даташиты
IDT 79RC32438
DMA Controller
– 10 DMA channels: two channels for PCI (PCI to Memory and
Memory to PCI), two for each Ethernet interface, two channels
for memory to memory operations, two channels for external
operations
– Provides flexible descriptor based operation
– Supports unaligned transfers (i.e., source or destination
address may be on any byte boundary) with arbitrary byte
length.
Two Ethernet Interfaces
– 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
– Two IEEE 802.3u compatible Media Independent Interfaces
(MII) with serial management interface
– MII supports IEEE 802.3u auto-negotiation speed selection
– Supports 64 entry hash table based multicast address filtering
www.DataSheet4U.c5o1m2 byte transmit and receive FIFOs
– Supports flow control functions outlined in IEEE Std. 802.3x-
1997
Universal Asynchronous Receiver Transmitter (UART)
– Compatible with the 16550 and 16450 UARTs
– Two completely separate serial channels
– Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)
– 16-byte transmit and receive buffers
– Programmable baud rate generator derived from the system
clock
– Fully programmable serial characteristics:
– 5, 6, 7, or 8 bit characters
– Even, odd or no parity bit generation and detection
– 1, 1-1/2 or 2 stop bit generation
– Line break generation and detection
– False start bit detection
– Internal loopback mode
I2C-Bus
– Supports standard 100 Kbps mode as well as 400 Kbps fast
mode
– Supports 7-bit and 10-bit addressing
– Supports four modes: master transmitter, master receiver,
slave transmitter, slave receiver
Additional General Purpose Peripherals
– Two 16550-compatible serial ports
– Interrupt controller
– System integrity functions
– General purpose I/O controller
– Serial peripheral interface (SPI)
On-chip Memory
– 4KB of high speed SRAM organized as 1K x 32 bits
– Supports burst and non-burst byte, halfword, triple-byte, and
word CPU, PCI, and DMA accesses
Debug Support
– Rev. 2.6 compliant EJTAG Interface
Device Overview
The RC32438 is a member of the IDT™ Interprise™ family of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
memory with minimal CPU intervention using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32438 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
CPU Execution Core
The 32-bit CPU core is 100% compatible with the MIPS32 instruction
set architecture (ISA).
Specifically, this device features the 4Kc CPU core developed by
MIPS Technologies Inc. (www.mips.com). This core issues a single
instruction per cycle, includes a five stage pipeline, and is optimized for
applications that require integer arithmetic. The CPU core includes 16
KB instruction and 16 KB data caches. Both caches are 4-way set asso-
ciative and can be locked on a per line basis, which allows the
programmer control over this precious on-chip memory resource. The
core also features a memory management unit (MMU). The CPU core
also incorporates an enhanced joint test access group (EJTAG) inter-
face that is used to interface to in-circuit emulator tools, providing
access to internal registers and enabling the part to be controlled exter-
nally, simplifying the system debug process. The use of this core allows
IDT's customers to leverage the broad range of software and develop-
ment tools available for the MIPS architecture, including operating
systems, compilers, and in-circuit emulators.
Double Data Rate Memory Controller
The RC32438 incorporates a high performance double data rate
(DDR) memory controller which supports both x16 and x32 memory
configurations up to 2GB. This module provides all of the signals
required to interface to both memory modules and discrete devices,
including two chip selects, differential clocking outputs and data strobes.
Memory and I/O Controller
The RC32438 uses a dedicated local memory/IO controller including
a de-multiplexed 16-bit data and 26-bit address bus. It includes all of the
signals required to interface directly to as many as six Intel or Motorola-
style external peripherals, and the interface can be configured to
support both 8-bit and 16-bit peripherals.
DMA Controller
The DMA controller consists of 10 independent DMA channels, all of
which operate in exactly the same manner. The DMA controller off-loads
the CPU core from moving data among the on-chip interfaces, external
peripherals, and memory. The controller supports scatter/gather DMA
with no alignment restrictions, appropriate for communications and
graphics systems.
PCI Interface
The PCI interface on the RC32438 is compatible with version 2.2 of
the PCI specification. An on-chip arbiter supports up to six external bus
masters, supporting both fixed priority and rotating priority arbitration
schemes. The part can support both satellite and host PCI configura-
tions, enabling the RC32438 to act as a slave controller for a PCI add-in
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79RC32438 Даташит, Описание, Даташиты
IDT 79RC32438
card application, or as the primary PCI controller in the system. The PCI
interface can be operated synchronously or asynchronously to the other
I/O interfaces on the RC32438 device.
Ethernet Interface
The RC32438 has two Ethernet Channels supporting 10Mbps and
100Mbps speeds to provide a standard media independent interface
(MII) off-chip, allowing a wide range of external devices to be connected
efficiently.
UART Interface
The RC32438 contains two completely separate serial channels
(UARTs) that are compatible with the industry standard 16550 UART.
www.DataSheet4U.com
System Integrity Functions
The RC32438 contains a programmable watchdog timer that gener-
ates NMI when the counter expires and an address space monitor that
reports errors in response to accesses to undecoded address regions.
General Purpose I/O Controller
The RC32438 contains 32 general purpose input/output pins. Each
pin may be used as an active high or active low level interrupt or non-
maskable interrupt input, and each signal may be used as a bit input or
output port.
I2C Interface
The standard I2C interface allows the RC32438 to connect to a
number of standard external peripherals for a more complete system
solution. The RC32438 supports both master and slave operations.
Debug Support
The RC32438 supports the industry standard Rev. 2.6 EJTAG inter-
face.
Thermal Considerations
The RC32438 consumes less than 2.7 W peak power. It is guaran-
teed in a ambient temperature range of 0° to +70° C for commercial
temperature devices and - 40° to +85° for industrial temperature
devices.
Revision History
November 7, 2002: Initial publication. Preliminary Information.
November 15, 2002: Added footnotes to Tables 5, 9, and 10.
December 12, 2002: Added Clock Speed parameter to PLL and
Core supply in Table 16.
December 19, 2002: Release version.
January 13, 2003: Changed Thermal Considerations to read less
than 2.7W instead of 2.5W, added values to CLK parameter in Table 5,
and revised EJTAG description.
February 4, 2003: Revised description for EJTAG/JTAG pins in
Table 1. Changed DDRDM[7:0] from input/output to output only in Tables
1 and 2 and Logic Diagram. Added new section, Voltage Sense Signal
Timing, as part of EJTAG description.
March 4, 2003: In Table 2, removed “pull-up” from PCI pin category
and from GPIO [24] and GPIO[30-26]. In Table 20, changed max. values
for VccSI/O, VccCore, and VccPLL.
July 9, 2003: In Table 7: changed values for DDRDATA, DDRDM,
and DDRADDR—WEN signals, and deleted old footnote #3 and
changed values in new footnote #3. In Table 8, changed Tdo values.
Changed Figure 7. Changed values in Table 18, Power Consumption.
Removed IPBus Monitor feature which included changes to Tables 1, 2,
21, 24, and 25. Deleted Table 13 which resulted in a re-ordering of
subsequent tables.
March 8, 2004: Added 300MHz speed grade.
May 25, 2004: In Table 9, signals MIIxRXCLK and MIIxTXCLK, the
Min and Max values for Thigh/Tlow_9c were changed to 140 and 260
respectively and the Min and Max values for Thigh/Tlow_9d were
changed to 14.0 and 26.0 respectively.
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May 25, 2004










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Номер в каталогеОписаниеПроизводители
79RC32435IDTTM InterpriseTM Integrated Communications ProcessorIntegrated Device Technology
Integrated Device Technology
79RC32435IDTTM InterpriseTM Integrated Communications ProcessorIntegrated Device Technology
Integrated Device Technology
79RC32438IDTTM InterpriseTM Integrated Communications ProcessorIntegrated Device Technology
Integrated Device Technology

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