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MT45W2MW16PFA PDF даташит

Спецификация MT45W2MW16PFA изготовлена ​​​​«Micron Semiconductor» и имеет функцию, называемую «(MT45WxMx16PFA) Async Cellularram Memory».

Детали детали

Номер произв MT45W2MW16PFA
Описание (MT45WxMx16PFA) Async Cellularram Memory
Производители Micron Semiconductor
логотип Micron Semiconductor логотип 

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MT45W2MW16PFA Даташит, Описание, Даташиты
www.DataSheet4U.com
PRELIMINARY
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
ASYNCHRONOUS
CellularRAMTM
MT45W4MW16PFA MT45W2MW16PFA
MT45W4MV16PFA MT45W2MV16PFA
MT45W4ML16PFA MT45W2ML16PFA
For the latest data sheet, please refer to Micron’s Web site:
www.micron.com/datasheets
Features
• Asynchronous and Page Mode interface
• Random Access Time: 70ns, 85ns
• Page Mode Read Access
Sixteen-word page size
Interpage read access: 70ns, 85ns
Intrapage read access: 20ns, 25ns
• VCC, VCCQ Voltages
1.70V–1.95V VCC
1.70V–2.25V VCCQ (Option W)
2.30V–2.70V VCCQ (Option V)
2.70V–3.30V VCCQ (Option L)
• Low Power Consumption
Asynchronous READ < 25mA
Intrapage READ < 15mA
Standby: 90µA (32Mb), 100µA (64Mb)
Deep Power-Down < 10µA
• Low-Power Features
Temperature Compensated Refresh (TCR)
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
Figure 1: 48-Ball FBGA
123456
A LB# OE# A0 A1 A2 ZZ#
B DQ8 UB# A3 A4 CE# DQ0
C DQ9 DQ10 A5 A6 DQ1 DQ2
D
VSSQ DQ11 A17
A7
DQ3
VCC
E VCCQ DQ12 A21 A16 DQ4 VSS
F DQ14 DQ13 A14 A15 DQ5 DQ6
G DQ15 A19 A12 A13 WE# DQ7
H A18 A8 A9 A10 A11 A20
Options
• VCC Core Voltage Supply
1.8V – MT45WxMx16PFA
• VCCQ I/O Voltage
3.0V – MT45WxML16PFA
2.5V – MT45WxMV16PFA
1.8V – MT45WxMW16PFA
• Access Time
60ns
70ns
85ns
• Configuration
4 Meg x 16
2 Meg x 16
• Package
48-ball FBGA
• Operating Temperature Range
Wireless (-25°C to +85°C)
Industrial (-40°C to +85°C)
Marking
W
L
V
W
(contact factory)
-70
-85
MT45W4Mx16PFA
MT45W2Mx16PFA
FA
WT
IT (contact factory)
Top View
(Bump Down)
NOTE:
See Table 1 on page 3 for Ball Descriptions. See Figure 18
on page 22 for the 48-ball mechanical drawing.
NOTE:
A part marking guide for the FBGA devices can be found
on Micron’s Web site: www.micron.com/numberguide.
Part Number Example:
MT45W2ML16PFA-70WT
09005aef80be1f7f
AsyncCellularRAM.fm - Rev. A 7/03 EN
1 ©2003 Micron Technology, Inc. All Rights Reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.









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MT45W2MW16PFA Даташит, Описание, Даташиты
www.DataSheet4U.com
PRELIMINARY
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
General Description
MicronCellularRAMproducts are high-speed,
CMOS dynamic random access memories that have
been developed for low-power portable applications.
The MT45W4Mx16PFA is a 64Mb device organized as 4
Meg x 16 bits, and the MT45W2Mx16PFA is a 32Mb
device organized as 2 Meg x 16 bits. These devices
include the industry-standard, asynchronous memory
interface found on other low-power SRAM or Pseudo
SRAM offerings.
Operating voltages have been reduced in an effort to
minimize power consumption. The core voltage has
been reduced to a 1.80V operating level. To maintain
compatibility with different memory bus interfaces,
CellularRAM devices are available with I/O voltages of
3.00V, 2.50V or 1.80V.
A user-accessible configuration register (CR) has
been included to define device operation. The CR
defines how the CellularRAM device performs on-chip
refresh and whether page mode read accesses are per-
mitted. This register is automatically loaded with a
default setting during power-up and can be updated at
any time during normal operation.
To operate seamlessly on an asynchronous memory
bus, CellularRAM products have incorporated a trans-
parent self refresh mechanism. The hidden refresh
requires no additional support from the system mem-
ory controller and has no significant impact on device
read/write performance.
Special attention has been focused on current con-
sumption during self refresh. CellularRAM products
include three system-accessible mechanisms used to
minimize refresh current. Temperature compensated
refresh (TCR) is used to adjust the refresh rate accord-
ing to the case temperature. The refresh rate can be
decreased at lower temperatures to minimize current
consumption during standby. Setting the sleep enable
pin ZZ# to LOW enables one of two low-power modes:
partial array refresh (PAR); or deep power-down
(DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts
refresh operation altogether and is used when no vital
information is stored in the device. These three refresh
mechanisms are accessed through the CR.
A[20:0]
(for 32Mb)
A[21:0]
(for 64Mb)
Figure 2: Functional Block Diagram
4 Meg x 16 and 2 Meg x 16
Address Decode
Logic
Configuration
Register (CR)
2,048K x 16
(4,096K x 16)
DRAM
MEMORY
ARRAY
Input/
Output
MUX
and
Buffers
DQ[7:0]
DQ[15:8]
CE#
WE#
OE#
UB#
LB#
ZZ#
Control
Logic
NOTE:
Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing
diagrams for detailed information.
09005aef80be1f7f
AsyncCellularRAM.fm - Rev. A 7/03 EN
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All Rights Reserved.









No Preview Available !

MT45W2MW16PFA Даташит, Описание, Даташиты
www.DataSheet4U.com
PRELIMINARY
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
Table 1: FBGA Ball Descriptions
FBGA BALL
ASSIGNMENT SYMBOL
A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3, H1, G2,
H6, E3
A6
A[21:0]
ZZ#
B5 CE#
A2 OE#
G5
A1
B2
B6, C5, C6, D5,
E5, F5, F6, G6,
B1, C1, C2, D2,
E2, F2, F1, G1
D6
E1
E6
D1
WE#
LB#
UB#
DQ[15:0]
VCC
VCCQ
VSS
VSSQ
TYPE
Input
Input
Input
Input
Input
Input
Input
Input/
Output
Supply
Supply
Supply
Supply
DESCRIPTION
Address Inputs: Inputs for the address accessed during READ or WRITE operations.
The address lines are also used to define the value to be loaded into the
configuration register. On the 32Mb device, A21 (ball E3) is not internally
connected.
Sleep Enable: When ZZ# is LOW, the configuration register can be loaded or the
device can enter one of two low-power modes (DPD or PAR).
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Enables WRITE operations when LOW.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.8V, 2.5V, 3.0V) Power supply for input/output buffers.
VSS must be connected to ground.
VSSQ must be connected to ground.
Table 2: Bus Operations
MODE
Standby
Read
Write
Active
PAR
DPD
Load
Configuration
Register
POWER
Standby
Active > Standby
Active > Standby
Standby
Partial Array Refresh
Deep Power-Down
Active
CE#
H
L
L
L
H
H
L
WE#
X
H
L
H
X
X
L
OE#
X
L
X
H
X
X
X
LB#/UB#
X
L
L
L
X
X
X
ZZ#
H
H
H
H
L
L
L
DQ[15:0]1
High-Z
Data-Out
Data-In
High-Z
High-Z
High-Z
High-Z
NOTES
2, 5
1, 4
1, 3, 4
4, 5
6
6
NOTE:
1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only DQ[7:0]
are affected. When UB# only is in the select mode, DQ[15:8] are affected.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are inter-
nally isolated from any external influence.
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. VIN = VCC or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
09005aef80be1f7f
AsyncCellularRAM.fm - Rev. A 7/03 EN
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All Rights Reserved.










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Номер в каталогеОписаниеПроизводители
MT45W2MW16PFA(MT45WxMx16PFA) Async Cellularram MemoryMicron Semiconductor
Micron Semiconductor

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