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HYM71V16635ALT8 PDF даташит

Спецификация HYM71V16635ALT8 изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «PC133 SDRAM Unbuffered DIMM».

Детали детали

Номер произв HYM71V16635ALT8
Описание PC133 SDRAM Unbuffered DIMM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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HYM71V16635ALT8 Даташит, Описание, Даташиты
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16Mx64bits
PC133 SDRAM Unbuffered DIMM
based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16635AT8 Series
DESCRIPTION
The Hynix HYM71V16635AT8 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bits
CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy
printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM71V16635AT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes
memory. The Hynix HYM71V16635AT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width.
FEATURES
• PC133/PC100MHz support
• 168pin SDRAM Unbuffered DIMM
• Serial Presence Detect with EEPROM
• SDRAM internal banks : four banks
• Module bank : one physical bank
• Auto refresh and self refresh
• 1.25” (31.75mm) Height PCB with single sided com- • 4096 refresh cycles / 64ms
ponents
• Programmable Burst Length and Burst Type
• Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
• All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
• Data mask function by DQM
• Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HYM71V16635AT8-K
HYM71V16635AT8-H
HYM71V16635ALT8-K
HYM71V16635ALT8-H
Clock
Frequency
Internal
Bank
133MHz
4 Banks
Ref.
4K
Power
Normal
Low Power
SDRAM
Package
Plating
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev.1.5/Dec.01
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HYM71V16635ALT8 Даташит, Описание, Даташиты
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PIN DESCRIPTION
PC133 SDRAM Unbuffered DIMM
HYM71V16635AT8 Series
PIN
CK0~CK3
CKE0
/S0, /S2
BA0, BA1
A0 ~ A11
/RAS, /CAS, /WE
DQM0~DQM7
DQ0 ~ DQ63
VCC
VSS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
/RAS, /CAS and /WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Ground
Serial Presence Detect Clock input
Serial Presence Detect Data input/output
Serial Presence Detect Address Input
Write Protect for Serial Presence Detect on DIMM
No connection
Rev. 1.5/Dec. 01
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PIN ASSIGNMENTS
PC133 SDRAM Unbuffered DIMM
HYM71V16635AT8 Series
FRONT SIDE
BACK SIDE
FRONT SIDE
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NAME
PIN NO.
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
85
86
87
88
89
90
91
92
93
94
Architecture Key
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
NC
NC
VSS
NC
NC
VCC
/WE
DQM0
DQM1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VCC
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
Voltage Key
NAME
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
NC
NC
VSS
NC
NC
VCC
/CAS
DQM4
DQM5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
PIN NO.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NAME
VCC
CK0
VSS
NC
/S2
DQM2
DQM3
NC
VCC
NC
NC
NC
NC
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
WP
SDA
SCL
VCC
Note : * CK1 and CK3 are connected with termination R/C (Refer to the block diagram)
BACK SIDE
PIN NO.
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NAME
*CK1
NC
VSS
CKE0
NC
DQM6
DQM7
NC
VCC
NC
NC
NC
NC
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
*CK3
NC
SA0
SA1
SA2
VCC
Rev. 1.5/Dec. 01
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