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PDF PT7C4302 Data sheet ( Hoja de datos )
| Número de pieza | PT7C4302 | |
| Descripción | Real-time Clock Module | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PT7C4302
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Real-time Clock Module (3-wire Interface)
Features
Using external 32.768kHz quartz crystal
Real-time clock (RTC) counts seconds, minutes
hours, date of the month, month, day of the week,
and year with leap-year compensation valid up to
2099
31-byte, nonvolatile (NV) RAM for data storage
Time keeping voltage: 1.5V to 5.5V
Uses less than 300nA at 2.0V
Simple 3-wire interface
Serial I/O for minimum pin count
Burst mode for reading/writing successive addresses
in clock/RAM
TTL-compatible (VCC = 5V)
Optional industrial temperature range: -40°C to
+85°C
Battery backup
Trickle charger on chip for rechargeable energy
source backup
Description
The PT7C4302 serial real-time clock is a low-
power clock/calendar with a programmable square-wave
output and 31 bytes of nonvolatile RAM.
Address and data are transferred serially via a 3-
wire bus. The clock/calendar provides seconds, minutes,
hours, day, date, month, and year information. The date
at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections
for leap year. The clock operates in either the 24-hour or
12-hour format with AM/PM indicator.
Table 1 shows the basic functions of PT7C4302.
More details are shown in section: overview of functions.
Pin Assignment
PT7C4302
1 VCC2
VCC1 8
2 X1
SCLK 7
3 X2
I/O 6
4 GND
RST 5
Pin Description
DIP-8
SOIC-8
Pin no. Pin Type
Description
1
VCC
2
P
Primary power. When VCC2 is greater than VCC1 + 0.2V, VCC2 will power the IC. While VCC2<VCC1, VCC1
will power the IC.*1
2 X1 I Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them.
3 X2 O Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them.
4 GND P Ground.
5
RST
I
Reset. The reset signal must be asserted high during a read or a write. This pin has a 40kΩ internal pull-
down resistor.
6
I/O
I/ Serial Data Input/Output. I/O is the input/output pin for the 3-wire serial interface. The pin has a 40k
O internal pull-down resistor.
7
SCL
K
I
Serial Clock Input. SCLK is used to synchronize data movement on the 3-wire serial interface. The pin
has a 40k internal pull-down resistor.
8
VCC
1
P
Backup power. When VCC2 is greater than VCC1 + 0.2V, VCC2 will power the IC. While VCC2<VCC1, VCC1
will power the IC. *1
Note*1: If VCC1 connects to battery, the battery voltage VCC1 has to be lower than VCC2 - 0.2Vwhen IC is read and written.
2015-11-0004
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PT7C4302
Real-time Clock Module (3-wire Interface)
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Recommended Layout for Crystal
Note: The crystal, traces and crystal input pins
should be isolated from RF generating signals.
Built-in Capacitors Specifications and Recommended External Capacitors
Parameter
Symbol
Typ
Unit
Build-in capacitors
X1 to GND
X2 to GND
CG
CD
11
11
pF
pF
Recommended External capacitors for
X1 to GND
C1
12
pF
crystal CL=12.5pF
X2 to GND
C2
12
pF
Recommended External capacitors for
X1 to GND
C1
0
pF
crystal CL=6pF
X2 to GND
C2
0
pF
Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768 KHz, C1 and C2 should
meet the equation as below:
Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL
Cpar is all parasitical capacitor between X1 and X2.
CL is crystal’s load capacitance.
Crystal Specifications
Parameter
Nominal Frequency
Series Resistance
Load Capacitance
Symbol
fO
ESR
CL
Min
-
-
-
Typ
32.768
-
6/12.5
Max
-
70
-
Unit
kHz
k
pF
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PT7C4302
Real-time Clock Module (3-wire Interface)
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c) Single Byte Read
Figure 2 Single byte read
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK
cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written.
Additional SCLK cycles will transmit the same data bytes by PT7C4302 so long as RST remains high. This operation permits
continuous burst mode read capability. Also, the SDA pin is tri-stated upon each rising edge of SCLK. Data is output starting with
bit 0.
d) Single Byte Write
Figure 3 Signal byte write
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK
cycles. Additional SCLK cycles are ignored. Data is input starting with bit 0.
e) Burst Mode
Burst mode is specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (Address bits: A4 A3
A2 A1 A0 = 1 1 1 1 1 showed in Figure 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no
data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or
writes in burst mode start with bit 0 of address 0.
When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred.
If the number of transferred bytes is less than eight, the data will be ignored. However, when writing to RAM in burst mode, it is
not necessary to write all 31 bytes for the data to transfer. Each byte that is written will be transferred to RAM regardless of
whether all 31 bytes are written or not. Additional SCLK cycles are ignored.
Clock/Calendar Burst Mode
The clock/calendar command byte specifies burst mode operation. In this mode the first eight clock/calendar registers can be
consecutively read or written starting with bit 0 of address 0.
If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the
eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode.
At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read
from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an
update of the main registers during a read.
RAM Burst Mode
The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written
starting with bit 0 of address 0.
Note: PT7C4302 use 94H, 96H as test mode address. Customer should not use the address.
2015-11-0004
PT0225-6 11/25/15
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet PT7C4302.PDF ] | |
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