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PDF PT7C4300 Data sheet ( Hoja de datos )
| Número de pieza | PT7C4300 | |
| Descripción | Real-time Clock Module | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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Data Sheet
PT7C4300
Real-time Clock Module (I2C Bus)
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Features
Description
• Using external 32.768kHz quartz crystal
• Supports I2C-Bus's high speed mode (400 kHz)
• Includes time (Hour/Minute/Second) and calendar
(Year/Month/Date/Day) counter functions (BCD
code)
• Automatic power-fail detect and switch circuitry of
battery backup
• Operating range: 2.0V to 5.5V
• Software clock calibration
• Ultra-low battery supply current of 1µA
The PT7C4300 serial real-time clock is a low-power
clock/calendar with a programmable square-wave output.
Address and data are transferred serially via a 2-wire
bidirectional bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in the 24-
hour format indicator.
Ordering Information
Part Number
PT7C4300W
PT7C4300WE
Package
8-Pin SOIC
Lead free 8-Pin SOIC
Table 1 shows the basic functions of PT7C4300. More
details are shown in section: overview of functions.
Table 1. Basic functions of PT7C4300
Item
Function
Source: Crystal: 32.768kHz
1 Oscillator Oscillator enable/disable
Oscillator fail detect
2 Time
Time display
Century bit
12-hour
24-hour
Time count chain enable/disable
3 Programmable square wave output (Hz)
4 Programmable high/low level output
2-wire I2C bus
Communicat
5
ion
3-wire bus
Burst mode
6 Battery backup
7 Clock calibration
PT7C4300
√
√
-
-
√
√
√
512Hz
√
√
-
-
√
√
PT0222(02/06)
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Ver: 0
1 page  
Data Sheet
PT7C4300
Real-time Clock Module (I2C Bus)
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Registers
1. Allocation of registers
Addr.
(hex) *1
Function
Register definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
00 Seconds (00-59)
ST*2
S40
S20 S10
S8
S4 S2 S1
01 Minutes (00-59)
× M40 M20 M10 M8 M4 M2 M1
02 Hours (00-23)
CEB*3
CB*3
H20
H10
H8
H4 H2 H1
03 Days of the week (01-07)
×
×
×
×
× W4 W2 W1
04 Dates (01-31)
×
×
D20 D10
D8
D4 D2 D1
05 Months (01-12)
× × ×*8 MO10 MO8 MO4 MO2 MO1
06 Years (00-99)
Y80 Y40 Y20 Y10 Y8
Y4 Y2 Y1
07 Control*3
OUT*4
FT*5
S*6
Calibration*7
Caution points:
*1. PT7C4300 uses 3 bits for address. That is if write data to 08H, the data will be written to 00H address register.
*2. Stop bit. When this bit is set to 1, oscillator and time count chain are both stopped.
*3. CEB: Century Enable Bit. CB: Century Bit.
*4. Control FT/OUT pin output DC level when 512Hz square wave is disabled.
*5. Frequency Test. 512Hz square wave output is enabled at FT/OUT pin, which is using for frequency test.
*6. Sign Bit. “1” indicates positive calibration; “0”indicates negative calibration.
*7. Using for modifying count frequency. If 20ppm is wanted to slow down the count frequency, 10 (01010) should be loaded.
Calibration will not affect FT/OUT output frequency.
*8. Don’t care.
PT0222(02/06)
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Ver: 0
5 Page 
Data Sheet
PT7C4300
Real-time Clock Module (I2C Bus)
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a) Write via I2C bus
S
Slave address (7 bits)
write A
11 0 1 00 0 0
Addr. setting
Start
Slave address + write specification
A
C Address
K Specifies the write start address.
A
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
A
P
A
C Write data
K
A Stop
C
K
b) Read via I2C bus
• Standard read
S
Slave address (7 bits)
write A
110 100 00
Addr. setting
Start
Slave address + write specification
A
C Address
K Specifies the read start address.
A
A
C
K
Sr
Slave address (7 bits)
Read A
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
11 0 1 00 0 1
Restart
Slave address + read specification
A
C Data read (1)
K Data is read from the specified start
address and address auto increment.
A
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
/A
P
A
C Data read (2)
K Address auto increment to set the
address for the next data to be read.
N Stop
O
A
C
K
• Simplified read
S
Slave address (7 bits)
Read A
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
A
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
/A
P
11 0 1 00 0 1
Start Slave address + read specification
A
C
K
Data read (1)
Data is read from the address pointed
by the internal address register and
address auto increment.
A
C
K
Data read (2)
Address register auto increment to set
N Stop
O
the address for the next data to be
A
read.
C
K
Note:
1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred
during actual communications.
2. 49H, 4AH are used as test mode address. Customer should not use the addresses.
PT0222(02/06)
11
Ver: 0
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet PT7C4300.PDF ] | |
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