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SY89228U PDF даташит

Спецификация SY89228U изготовлена ​​​​«Micrel Semiconductor» и имеет функцию, называемую «Clock Divider».

Детали детали

Номер произв SY89228U
Описание Clock Divider
Производители Micrel Semiconductor
логотип Micrel Semiconductor логотип 

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SY89228U Даташит, Описание, Даташиты
www.DataSheet4U.com
SY89228U
1GHz Precision, LVPECL ÷3, ÷5 Clock Divider
with Fail-Safe Input and Internal Termination
General Description
The SY89228U is a precision, low jitter 1GHz ÷3, ÷5
clock divider with an LVPECL output. A unique Fail-
Safe Input (FSI) protection prevents metastable
output conditions when the input clock voltage swing
drops significantly below 100mV or input is removed.
The differential input includes Micrel’s unique, 3-pin
internal termination architecture that allows the input
to interface to any differential signal (AC- or DC-
coupled) as small as 100mV (200mVPP) without any
level shifting or termination resistor networks in the
signal path. The outputs are 800mV, 100K-
compatible LVPECL with fast rise/fall times
guaranteed to be less than 270ps.
The SY89228U operates from a 2.5V ±5% or 3.3V
±10% supply and is guaranteed over the full
industrial temperature range of –40°C to +85°C. The
SY89228U is part of Micrel’s high-speed, Precision
Edge® product line.
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
Block Diagram
Features
Precision Edge®
Accepts a high-speed input and provides a precision
÷3 and ÷5 sub-rate, LVPECL output
Fail-Safe Input
– Prevents oscillations when input is invalid
Guaranteed AC performance over temperature and
supply voltage:
– DC-to >1.0GHz throughput
– < 1500ps Propagation Delay (In-to-Q)
– < 270ps Rise/Fall times
Ultra-low jitter design:
– <1psRMS random jitter
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter (clock)
– <0.7psRMS MUX crosstalk induced jitter
Unique patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
Wide input voltage range VCC to GND
800mV LVPECL output
46% to 54% Duty Cycle(÷ 3)
47% to 53% Duty Cycle(÷ 5)
2.5V ±5% or 3.3V ±10% supply voltage
-40°C to +85°C industrial temperature range
Available in 16-pin (3mm x 3mm) MLF® package
Applications
Fail-safe clock protection
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-080707-A
[email protected] or (408) 955-1690









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SY89228U Даташит, Описание, Даташиты
Micrel, Inc.
Ordering Information(1)
Part Number
SY89228UMG
SY89228UMGTR(2)
Package
Type
MLF-16
MLF-16
Operating
Range
Industrial
Industrial
Package Marking
228U with
Pb-Free bar-line Indicator
228U with
Pb-Free bar-line Indicator
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only.
2. Tape and Reel.
SY89228U
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
16-Pin MLF® (MLF-16)
August 2007
2 M9999-080707-A
[email protected] or (408) 955-1690









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SY89228U Даташит, Описание, Даташиты
Micrel, Inc.
SY89228U
Pin Description
Pin Number
1, 4
2
3
5
6
7
8, 13
12, 9
10, 11, 14,15
16
Pin Name
IN, /IN
VT
VREF-AC
EN
/MR
NC
VCC
Q, /Q
GND,
Exposed Pad
DIV_SEL
Pin Function
Differential Input: This input pair is the differential signal input to the device, which
accepts AC- or DC-coupled signal as small as 100mV. The input internally terminates
to a VT pin through 50and has level shifting resistors of 3.72 kto VCC. This
allows a wide input voltage range from VCC to GND. See Figure 3a, Simplified
Differential Input Stage for details. Note that this input will default to a valid (either
HIGH or LOW) state if left open. See “Input Interface Applications” subsection.
Input Termination Center-Tap: Each side of the differential input pair terminates to
the VT pin. The VT pin provides a center-tap for the input (IN, /IN) to a termination
network for maximum interface flexibility. See “Input Interface Applications”
subsection for more details.
Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling inputs
IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR
capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to
drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input
Interface Applications” subsection.
Single-ended Input: This TTL/CMOS-compatible input disables and enables the
output. It is internally connected to a 25kpull-up resistor and will default to a logic
HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH. EN being
synchronous, outputs will be enabled/disabled after a rising and a falling edge of the
input clock. VTH = VCC/2.
Single-ended Input: This TTL/CMOS-compatible input, when pulled LOW,
asynchronously sets Q output LOW and /Q output HIGH. Note that this input is
internally connected to a 25kpull-up resistor and will default to logic HIGH state if
left open. VTH = VCC/2.
No Connect
Positive Power Supply: Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors
as close to the VCC pins as possible.
Differential Output: The LVPECL output swing is typically 800mV and is terminated
with 50to VCC-2V. See the “Truth Table” below for the logic function.
Ground: Ground and exposed pad must be connected to a ground plane that is the
same potential as the ground pins.
Single-ended Input: This TTL/CMOS-compatible input selects divide-by-3 when
pulled LOW and divide-by-5 when pulled HIGH. Note that this input is internally
connected to a 25kpull-up resistor and will default to logic HIGH state if left open.
VTH = VCC/2.
Truth Table
Inputs
Outputs
DIV_SEL EN /MR Q
/Q
X X 0 01
0 1 1 ÷3 ÷3
1 1 1 ÷5 ÷5
X 0 1 01
August 2007
3 M9999-080707-A
[email protected] or (408) 955-1690










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